diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrVSX.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 79 |
1 files changed, 55 insertions, 24 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 8321d7f2ecf..0f073388dc7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -1217,6 +1217,27 @@ def ScalarLoads { dag Li32 = (i32 (load xoaddr:$src)); } +def DWToSPExtractConv { + dag El0US1 = (f32 (PPCfcfidus + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); + dag El1US1 = (f32 (PPCfcfidus + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); + dag El0US2 = (f32 (PPCfcfidus + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); + dag El1US2 = (f32 (PPCfcfidus + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); + dag El0SS1 = (f32 (PPCfcfids + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); + dag El1SS1 = (f32 (PPCfcfids + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); + dag El0SS2 = (f32 (PPCfcfids + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); + dag El1SS2 = (f32 (PPCfcfids + (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); + dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2)); + dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2)); +} + // The following VSX instructions were introduced in Power ISA 2.07 /* FIXME: if the operands are v2i64, these patterns will not match. we should define new patterns or otherwise match the same patterns @@ -1452,35 +1473,27 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns. } // UseVSXReg = 1 let Predicates = [IsLittleEndian] in { - def : Pat<(f32 (PPCfcfids - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 0)))))), - (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; - def : Pat<(f32 (PPCfcfids - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), + def : Pat<DWToSPExtractConv.El0SS1, + (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; + def : Pat<DWToSPExtractConv.El1SS1, (f32 (XSCVSXDSP (COPY_TO_REGCLASS - (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; - def : Pat<(f32 (PPCfcfidus - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 0)))))), - (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; - def : Pat<(f32 (PPCfcfidus - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), + (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; + def : Pat<DWToSPExtractConv.El0US1, + (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; + def : Pat<DWToSPExtractConv.El1US1, (f32 (XSCVUXDSP (COPY_TO_REGCLASS - (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; + (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; } let Predicates = [IsBigEndian] in { - def : Pat<(f32 (PPCfcfids - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 0)))))), - (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S, VSFRC)))>; - def : Pat<(f32 (PPCfcfids - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), - (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; - def : Pat<(f32 (PPCfcfidus - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 0)))))), - (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S, VSFRC)))>; - def : Pat<(f32 (PPCfcfidus - (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), - (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; + def : Pat<DWToSPExtractConv.El0SS1, + (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; + def : Pat<DWToSPExtractConv.El1SS1, + (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; + def : Pat<DWToSPExtractConv.El0US1, + (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; + def : Pat<DWToSPExtractConv.El1US1, + (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; } // Instructions for converting float to i64 feeding a store. @@ -3814,6 +3827,15 @@ let AddedComplexity = 400 in { (XFLOADf32 xoaddr:$A), VSFRC)), 0))>; } + let Predicates = [IsBigEndian, HasP8Vector] in { + def : Pat<DWToSPExtractConv.BVU, + (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3), + (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>; + def : Pat<DWToSPExtractConv.BVS, + (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3), + (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>; + } + // Big endian, available on all targets with VSX let Predicates = [IsBigEndian, HasVSX] in { def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), @@ -3842,6 +3864,15 @@ let AddedComplexity = 400 in { (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>; } + let Predicates = [IsLittleEndian, HasP8Vector] in { + def : Pat<DWToSPExtractConv.BVU, + (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3), + (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>; + def : Pat<DWToSPExtractConv.BVS, + (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3), + (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>; + } + let Predicates = [IsLittleEndian, HasVSX] in { // Little endian, available on all targets with VSX def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), |
