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-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 655114b07f1..540d6932004 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2065,6 +2065,12 @@ bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
return true;
}
+#ifndef NDEBUG
+static bool isAnImmediateOperand(const MachineOperand &MO) {
+ return MO.isCPI() || MO.isGlobal() || MO.isImm();
+}
+#endif
+
bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
auto &MBB = *MI.getParent();
auto DL = MI.getDebugLoc();
@@ -2087,7 +2093,8 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case PPC::DFSTOREf64: {
assert(Subtarget.hasP9Vector() &&
"Invalid D-Form Pseudo-ops on Pre-P9 target.");
- assert(MI.getOperand(2).isReg() && MI.getOperand(1).isImm() &&
+ assert(MI.getOperand(2).isReg() &&
+ isAnImmediateOperand(MI.getOperand(1)) &&
"D-form op must have register and immediate operands");
return expandVSXMemPseudo(MI);
}
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