diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC.td | 55 |
1 files changed, 36 insertions, 19 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 279c430e1ce..ee3d6501fae 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -53,40 +53,52 @@ def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">; def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; -def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", - "Use software emulation for floating point">; +def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", + "Enable floating-point instructions">; def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", "Enable 64-bit registers usage for ppc32 [beta]">; def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", "Use condition-register bits individually">; def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", - "Enable Altivec instructions">; + "Enable Altivec instructions", + [FeatureHardFloat]>; def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", - "Enable SPE instructions">; + "Enable SPE instructions", + [FeatureHardFloat]>; def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", "Enable the MFOCRF instruction">; def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", - "Enable the fsqrt instruction">; + "Enable the fsqrt instruction", + [FeatureHardFloat]>; def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", - "Enable the fcpsgn instruction">; + "Enable the fcpsgn instruction", + [FeatureHardFloat]>; def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", - "Enable the fre instruction">; + "Enable the fre instruction", + [FeatureHardFloat]>; def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", - "Enable the fres instruction">; + "Enable the fres instruction", + [FeatureHardFloat]>; def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", - "Enable the frsqrte instruction">; + "Enable the frsqrte instruction", + [FeatureHardFloat]>; def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", - "Enable the frsqrtes instruction">; + "Enable the frsqrtes instruction", + [FeatureHardFloat]>; def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", "Assume higher precision reciprocal estimates">; def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", - "Enable the stfiwx instruction">; + "Enable the stfiwx instruction", + [FeatureHardFloat]>; def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", - "Enable the lfiwax instruction">; + "Enable the lfiwax instruction", + [FeatureHardFloat]>; def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", - "Enable the fri[mnpz] instructions">; + "Enable the fri[mnpz] instructions", + [FeatureHardFloat]>; def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", - "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; + "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", + [FeatureHardFloat]>; def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", "Enable the isel instruction">; def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", @@ -112,7 +124,8 @@ def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", "Enable PPC 6xx instructions">; def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", - "Enable QPX instructions">; + "Enable QPX instructions", + [FeatureHardFloat]>; def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", "Enable VSX instructions", [FeatureAltivec]>; @@ -282,7 +295,8 @@ include "PPCInstrInfo.td" // PowerPC processors supported. // -def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>; +def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, + FeatureMFTB]>; def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, @@ -291,8 +305,8 @@ def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, FeatureMSYNC, FeatureMFTB]>; -def : Processor<"601", G3Itineraries, [Directive601]>; -def : Processor<"602", G3Itineraries, [Directive602, +def : Processor<"601", G3Itineraries, [Directive601, FeatureHardFloat]>; +def : Processor<"602", G3Itineraries, [Directive602, FeatureHardFloat, FeatureMFTB]>; def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES, FeatureFRSQRTE, @@ -406,7 +420,10 @@ def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; // FIXME: Same as P8 until the POWER9 scheduling info is available def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>; -def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>; +def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, + FeatureMFTB]>; +def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, + FeatureMFTB]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, |
