diff options
Diffstat (limited to 'llvm/lib/Target/Mips')
5 files changed, 21 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 62715600583..512267320c1 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" @@ -211,7 +212,7 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCObjectWriter * MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { - return createMipsELFObjectWriter(OS, TheTriple); + return createMipsELFObjectWriter(OS, TheTriple, IsN32); } // Little-endian fixup data byte ordering: @@ -473,3 +474,10 @@ bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { OW->WriteZeros(Count); return true; } + +MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, + const MCRegisterInfo &MRI, + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { + return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32"); +} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index e2305bd27f0..409d4e2bf92 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -30,11 +30,12 @@ class Target; class MipsAsmBackend : public MCAsmBackend { Triple TheTriple; bool IsLittle; // Big or little endian + bool IsN32; public: MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, - StringRef CPU) - : TheTriple(TT), IsLittle(TT.isLittleEndian()) {} + StringRef CPU, bool N32) + : TheTriple(TT), IsLittle(TT.isLittleEndian()), IsN32(N32) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index 469e598f4b3..5c78799996f 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -657,12 +657,10 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, } MCObjectWriter *llvm::createMipsELFObjectWriter(raw_pwrite_stream &OS, - const Triple &TT) { + const Triple &TT, bool IsN32) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - // FIXME: We need to check an actual ABI. mips64/mips64el do not - // always imply the N64 ABI and RELA relocation's format. - bool IsN64 = TT.isArch64Bit(); - bool HasRelocationAddend = IsN64; + bool IsN64 = TT.isArch64Bit() && !IsN32; + bool HasRelocationAddend = TT.isArch64Bit(); auto *MOTW = new MipsELFObjectWriter(OSABI, HasRelocationAddend, IsN64, TT.isLittleEndian()); return createELFObjectWriter(MOTW, OS, TT.isLittleEndian()); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 7609ff2d69e..e05cbc55ffe 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -183,7 +183,7 @@ extern "C" void LLVMInitializeMipsTargetMC() { *T, createMipsObjectTargetStreamer); // Register the asm backend. - RegisterMCAsmBackend<MipsAsmBackend> Y(*T); + TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); } // Register the MC Code Emitter diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index c95efd6cd4b..3b46c5c4949 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -43,8 +43,12 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); +MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); + MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, - const Triple &TT); + const Triple &TT, bool IsN32); namespace MIPS_MC { StringRef selectMipsCPU(const Triple &TT, StringRef CPU); |
