summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index f471464b904..5a1c2c67cc7 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -70,13 +70,13 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
return;
MachineBasicBlock &MBB = MF.front();
- MachineBasicBlock::iterator I = MBB.begin();
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
- const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
- DebugLoc DL;
- unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
- const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
-
+ MachineBasicBlock::iterator I = MBB.begin();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+ DebugLoc DL;
+ unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
+ const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
+
V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC);
V2 = RegInfo.createVirtualRegister(RC);
OpenPOWER on IntegriCloud