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-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp5
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h4
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp12
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h6
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp12
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h4
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp20
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h12
8 files changed, 34 insertions, 41 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 03b5ca28c4a..bd1feb81d86 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -47,7 +47,7 @@ unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
llvm_unreachable("Unhandled ABI");
}
-MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU,
+MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
if (Options.getABIName().startswith("o32"))
return MipsABIInfo::O32();
@@ -64,8 +64,7 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU,
// used and not shared in a couple of other places. This needs unifying
// at some level.
if (CPU.empty() || CPU == "generic") {
- if (TT.getArch() == TargetTuple::mips ||
- TT.getArch() == TargetTuple::mipsel)
+ if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index d58e6abddd3..cb3df44c800 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -11,7 +11,7 @@
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -36,7 +36,7 @@ public:
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
- static MipsABIInfo computeTargetABI(const TargetTuple &TT, StringRef CPU,
+ static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
bool IsKnown() const { return ThisABI != ABI::Unknown; }
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index 13f90d434a3..328e71720ca 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -411,31 +411,27 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
// MCAsmBackend
MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
/*Is64Bit*/ false);
}
MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
/*Is64Bit*/ false);
}
MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
}
MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
/*Is64Bit*/ true);
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
index 603a58fb5de..b3d5a4964f8 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
@@ -16,7 +16,7 @@
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
#include "MCTargetDesc/MipsFixupKinds.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmBackend.h"
namespace llvm {
@@ -27,12 +27,12 @@ class Target;
class MCObjectWriter;
class MipsAsmBackend : public MCAsmBackend {
- TargetTuple::OSType OSType;
+ Triple::OSType OSType;
bool IsLittle; // Big or little endian
bool Is64Bit; // 32 or 64 bit words
public:
- MipsAsmBackend(const Target &T, TargetTuple::OSType OSType, bool IsLittle,
+ MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
bool Is64Bit)
: MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
index c370c816ac7..4d554583dc7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
@@ -12,19 +12,19 @@
//===----------------------------------------------------------------------===//
#include "MipsMCAsmInfo.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
using namespace llvm;
void MipsMCAsmInfo::anchor() { }
-MipsMCAsmInfo::MipsMCAsmInfo(const TargetTuple &TT) {
- if ((TT.getArch() == TargetTuple::mips) ||
- (TT.getArch() == TargetTuple::mips64))
+MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
+ if ((TheTriple.getArch() == Triple::mips) ||
+ (TheTriple.getArch() == Triple::mips64))
IsLittleEndian = false;
- if ((TT.getArch() == TargetTuple::mips64el) ||
- (TT.getArch() == TargetTuple::mips64)) {
+ if ((TheTriple.getArch() == Triple::mips64el) ||
+ (TheTriple.getArch() == Triple::mips64)) {
PointerSize = CalleeSaveStackSlotSize = 8;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
index f7ad1f6dc5e..d4ccf0349c1 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
@@ -17,13 +17,13 @@
#include "llvm/MC/MCAsmInfoELF.h"
namespace llvm {
-class TargetTuple;
+class Triple;
class MipsMCAsmInfo : public MCAsmInfoELF {
void anchor() override;
public:
- explicit MipsMCAsmInfo(const TargetTuple &TT);
+ explicit MipsMCAsmInfo(const Triple &TheTriple);
};
} // namespace llvm
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index 5ef473099d1..949ee1474f9 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -17,7 +17,7 @@
#include "MipsMCNaCl.h"
#include "MipsMCTargetDesc.h"
#include "MipsTargetStreamer.h"
-#include "llvm/ADT/TargetTuple.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -43,10 +43,9 @@ using namespace llvm;
/// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsSubtarget.cpp
-StringRef MIPS_MC::selectMipsCPU(const TargetTuple &TT, StringRef CPU) {
+StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
if (CPU.empty() || CPU == "generic") {
- if (TT.getArch() == TargetTuple::mips ||
- TT.getArch() == TargetTuple::mipsel)
+ if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
@@ -60,20 +59,20 @@ static MCInstrInfo *createMipsMCInstrInfo() {
return X;
}
-static MCRegisterInfo *createMipsMCRegisterInfo(const TargetTuple &TT) {
+static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitMipsMCRegisterInfo(X, Mips::RA);
return X;
}
-static MCSubtargetInfo *createMipsMCSubtargetInfo(const TargetTuple &TT,
+static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU);
return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
}
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
- const TargetTuple &TT) {
+ const Triple &TT) {
MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
@@ -83,8 +82,7 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}
-static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT,
- Reloc::Model RM,
+static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -96,7 +94,7 @@ static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT,
return X;
}
-static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T,
+static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
@@ -104,7 +102,7 @@ static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T,
return new MipsInstPrinter(MAI, MII, MRI);
}
-static MCStreamer *createMCStreamer(const TargetTuple &T, MCContext &Context,
+static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
MCAsmBackend &MAB, raw_pwrite_stream &OS,
MCCodeEmitter *Emitter, bool RelaxAll) {
MCStreamer *S;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index 13f6e4045b0..4069d7d184e 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -26,7 +26,7 @@ class MCRegisterInfo;
class MCSubtargetInfo;
class StringRef;
class Target;
-class TargetTuple;
+class Triple;
class raw_ostream;
class raw_pwrite_stream;
@@ -44,22 +44,22 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI,
- const TargetTuple &TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit);
namespace MIPS_MC {
-StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU);
+StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
}
} // End llvm namespace
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