diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
8 files changed, 15 insertions, 16 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index c05fbc1d775..640a31bee4e 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -332,7 +332,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( // follow the duplex model, so the register values in the MCInst are // incorrect. If the instruction is a compound, loop through the // operands and change registers appropriately. - if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCOMPOUND) { + if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCJ) { for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { if (i->isReg()) { unsigned reg = i->getReg() - Hexagon::R0; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td index 493d04703da..6c8856d31df 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -17,10 +17,10 @@ // *** Must match BaseInfo.h *** //----------------------------------------------------------------------------// -def TypeV4LDST : IType<9>; +def TypeV4LDST : IType<9>; def TypeNV : IType<10>; def TypeDUPLEX : IType<11>; -def TypeCOMPOUND : IType<12>; +def TypeCJ : IType<12>; def TypePREFIX : IType<30>; // Duplex Instruction Class Declaration @@ -150,11 +150,11 @@ class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon; class CJInst_JMPSET<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCJ>, OpcodeHexagon; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index c2a8b569cde..28b6f7a8936 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1713,7 +1713,7 @@ bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const { // Return true if the instruction is a compund branch instruction. bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const { - return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch()); + return getType(MI) == HexagonII::TypeCJ && MI.isBranch(); } bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const { diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 18943a082d2..ed8c0353c20 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3056,7 +3056,7 @@ class CJInst_tstbit_R0<string px, bit np, string tnt> : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2), ""#px#" = tstbit($Rs, #0); if (" #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { + [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { bits<4> Rs; bits<11> r9_2; @@ -3102,7 +3102,7 @@ class CJInst_RR<string px, string op, bit np, string tnt> : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2), ""#px#" = cmp."#op#"($Rs, $Rt); if (" #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { + [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { bits<4> Rs; bits<4> Rt; bits<11> r9_2; @@ -3156,7 +3156,7 @@ class CJInst_RU5<string px, string op, bit np, string tnt> : InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2), ""#px#" = cmp."#op#"($Rs, #$U5); if (" #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { + [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { bits<4> Rs; bits<5> U5; bits<11> r9_2; @@ -3211,7 +3211,7 @@ class CJInst_Rn1<string px, string op, bit np, string tnt> : InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2), ""#px#" = cmp."#op#"($Rs,#$n1); if (" #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { + [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { bits<4> Rs; bits<11> r9_2; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index c140bd1d7ee..3bc238e84e2 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -524,8 +524,7 @@ public: bool Relaxable = false; // Branches and loop-setup insns are handled as necessary by relaxation. if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || - (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == - HexagonII::TypeCOMPOUND && + (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && MCID.isBranch()) || (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && MCID.isBranch()) || diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 4292f6b3faa..b4c35fd68b2 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -44,7 +44,7 @@ namespace HexagonII { TypeV4LDST = 9, TypeNV = 10, TypeDUPLEX = 11, - TypeCOMPOUND = 12, + TypeCJ = 12, TypeCVI_FIRST = 13, TypeCVI_VA = TypeCVI_FIRST, TypeCVI_VA_DV = 14, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 2645a17b9bd..cdabe8aa44c 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -126,7 +126,7 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction( " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" "\n"); - if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { + if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCJ) { for (unsigned i = 0; i < HMB.getNumOperands(); ++i) if (HMB.getOperand(i).isReg()) { unsigned Reg = diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index e627f026c8a..f975ecb1928 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -438,7 +438,7 @@ bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) { bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII, MCInst const &MCI) { - return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND); + return getType(MCII, MCI) == HexagonII::TypeCJ; } bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) { @@ -470,7 +470,7 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII, return true; // Branch insns are handled as necessary by relaxation. if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) || - (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND && + (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ && HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) || (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV && HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch())) |
