diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
33 files changed, 532 insertions, 500 deletions
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 1d15a272d7d..577513bd3c9 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -462,9 +462,9 @@ void HexagonOperand::print(raw_ostream &OS) const { } bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { - DEBUG(dbgs() << "Bundle:"); - DEBUG(MCB.dump_pretty(dbgs())); - DEBUG(dbgs() << "--\n"); + LLVM_DEBUG(dbgs() << "Bundle:"); + LLVM_DEBUG(MCB.dump_pretty(dbgs())); + LLVM_DEBUG(dbgs() << "--\n"); MCB.setLoc(IDLoc); // Check the bundle for errors. @@ -557,9 +557,9 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, canonicalizeImmediates(MCI); result = processInstruction(MCI, InstOperands, IDLoc); - DEBUG(dbgs() << "Insn:"); - DEBUG(MCI.dump_pretty(dbgs())); - DEBUG(dbgs() << "\n\n"); + LLVM_DEBUG(dbgs() << "Insn:"); + LLVM_DEBUG(MCI.dump_pretty(dbgs())); + LLVM_DEBUG(dbgs() << "\n\n"); MCI.setLoc(IDLoc); } @@ -1296,9 +1296,9 @@ unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, return Match_Success; } - DEBUG(dbgs() << "Unmatched Operand:"); - DEBUG(Op->dump()); - DEBUG(dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Unmatched Operand:"); + LLVM_DEBUG(Op->dump()); + LLVM_DEBUG(dbgs() << "\n"); return Match_InvalidOperand; } diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index 849bba987c3..4791b067aa8 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -2450,7 +2450,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI, if (Len == RW) return false; - DEBUG({ + LLVM_DEBUG({ dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) << ", MI: " << *MI; dbgs() << "Cell: " << RC << '\n'; @@ -2644,7 +2644,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) { const HexagonEvaluator HE(HRI, MRI, HII, MF); BitTracker BT(HE, MF); - DEBUG(BT.trace(true)); + LLVM_DEBUG(BT.trace(true)); BT.run(); MachineBasicBlock &Entry = MF.front(); @@ -2975,7 +2975,8 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB, } bool HexagonLoopRescheduling::processLoop(LoopCand &C) { - DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n"); + LLVM_DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) + << "\n"); std::vector<PhiInfo> Phis; for (auto &I : *C.LB) { if (!I.isPHI()) @@ -2999,7 +3000,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { Phis.push_back(PhiInfo(I, *C.LB)); } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Phis: {"; for (auto &I : Phis) { dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" @@ -3120,7 +3121,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { Groups.push_back(G); } - DEBUG({ + LLVM_DEBUG({ for (unsigned i = 0, n = Groups.size(); i < n; ++i) { InstrGroup &G = Groups[i]; dbgs() << "Group[" << i << "] inp: " @@ -3188,7 +3189,7 @@ bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); const HexagonEvaluator HE(*HRI, *MRI, *HII, MF); BitTracker BT(HE, MF); - DEBUG(BT.trace(true)); + LLVM_DEBUG(BT.trace(true)); BT.run(); BTP = &BT; diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp index 2fb30dfbc1c..48a4505458a 100644 --- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -422,10 +422,10 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeLiveMap( InstrIndexMap &IndexMap) { RegToRangeMap LiveMap; - DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n'); computeInitialLiveRanges(IndexMap, LiveMap); - DEBUG(dbgs() << __func__ << ": live map\n" - << PrintRangeMap(LiveMap, TRI) << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": live map\n" + << PrintRangeMap(LiveMap, TRI) << '\n'); return LiveMap; } @@ -486,8 +486,8 @@ HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeDeadMap( if (TargetRegisterInfo::isVirtualRegister(P.first.Reg)) addDeadRanges(P.first); - DEBUG(dbgs() << __func__ << ": dead map\n" - << PrintRangeMap(DeadMap, TRI) << '\n'); + LLVM_DEBUG(dbgs() << __func__ << ": dead map\n" + << PrintRangeMap(DeadMap, TRI) << '\n'); return DeadMap; } diff --git a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp index 3e6420c671f..2fa7888dd02 100644 --- a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -90,7 +90,7 @@ FunctionPass *llvm::createHexagonBranchRelaxation() { } bool HexagonBranchRelaxation::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "****** Hexagon Branch Relaxation ******\n"); + LLVM_DEBUG(dbgs() << "****** Hexagon Branch Relaxation ******\n"); auto &HST = MF.getSubtarget<HexagonSubtarget>(); HII = HST.getInstrInfo(); @@ -200,14 +200,14 @@ bool HexagonBranchRelaxation::reGenerateBranch(MachineFunction &MF, for (auto &MI : B) { if (!MI.isBranch() || !isJumpOutOfRange(MI, BlockToInstOffset)) continue; - DEBUG(dbgs() << "Long distance jump. isExtendable(" - << HII->isExtendable(MI) << ") isConstExtended(" - << HII->isConstExtended(MI) << ") " << MI); + LLVM_DEBUG(dbgs() << "Long distance jump. isExtendable(" + << HII->isExtendable(MI) << ") isConstExtended(" + << HII->isConstExtended(MI) << ") " << MI); // Since we have not merged HW loops relaxation into // this code (yet), soften our approach for the moment. if (!HII->isExtendable(MI) && !HII->isExtended(MI)) { - DEBUG(dbgs() << "\tUnderimplemented relax branch instruction.\n"); + LLVM_DEBUG(dbgs() << "\tUnderimplemented relax branch instruction.\n"); } else { // Find which operand is expandable. int ExtOpNum = HII->getCExtOpNum(MI); diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index 53803b85db8..073f3e56aaf 100644 --- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -342,7 +342,7 @@ bool HexagonCommonGEP::isHandledGepForm(GetElementPtrInst *GepI) { void HexagonCommonGEP::processGepInst(GetElementPtrInst *GepI, ValueToNodeMap &NM) { - DEBUG(dbgs() << "Visiting GEP: " << *GepI << '\n'); + LLVM_DEBUG(dbgs() << "Visiting GEP: " << *GepI << '\n'); GepNode *N = new (*Mem) GepNode; Value *PtrOp = GepI->getPointerOperand(); uint32_t InBounds = GepI->isInBounds() ? GepNode::InBounds : 0; @@ -426,7 +426,7 @@ void HexagonCommonGEP::collect() { } } - DEBUG(dbgs() << "Gep nodes after initial collection:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after initial collection:\n" << Nodes); } static void invert_find_roots(const NodeVect &Nodes, NodeChildrenMap &NCM, @@ -575,7 +575,7 @@ void HexagonCommonGEP::common() { } } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Gep node equality:\n"; for (NodePairSet::iterator I = Eq.begin(), E = Eq.end(); I != E; ++I) dbgs() << "{ " << I->first << ", " << I->second << " }\n"; @@ -642,7 +642,7 @@ void HexagonCommonGEP::common() { N->Parent = Rep; } - DEBUG(dbgs() << "Gep nodes after commoning:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after commoning:\n" << Nodes); // Finally, erase the nodes that are no longer used. NodeSet Erase; @@ -662,35 +662,35 @@ void HexagonCommonGEP::common() { NodeVect::iterator NewE = remove_if(Nodes, in_set(Erase)); Nodes.resize(std::distance(Nodes.begin(), NewE)); - DEBUG(dbgs() << "Gep nodes after post-commoning cleanup:\n" << Nodes); + LLVM_DEBUG(dbgs() << "Gep nodes after post-commoning cleanup:\n" << Nodes); } template <typename T> static BasicBlock *nearest_common_dominator(DominatorTree *DT, T &Blocks) { - DEBUG({ - dbgs() << "NCD of {"; - for (typename T::iterator I = Blocks.begin(), E = Blocks.end(); - I != E; ++I) { - if (!*I) - continue; - BasicBlock *B = cast<BasicBlock>(*I); - dbgs() << ' ' << B->getName(); - } - dbgs() << " }\n"; - }); + LLVM_DEBUG({ + dbgs() << "NCD of {"; + for (typename T::iterator I = Blocks.begin(), E = Blocks.end(); I != E; + ++I) { + if (!*I) + continue; + BasicBlock *B = cast<BasicBlock>(*I); + dbgs() << ' ' << B->getName(); + } + dbgs() << " }\n"; + }); - // Allow null basic blocks in Blocks. In such cases, return nullptr. - typename T::iterator I = Blocks.begin(), E = Blocks.end(); - if (I == E || !*I) + // Allow null basic blocks in Blocks. In such cases, return nullptr. + typename T::iterator I = Blocks.begin(), E = Blocks.end(); + if (I == E || !*I) + return nullptr; + BasicBlock *Dom = cast<BasicBlock>(*I); + while (++I != E) { + BasicBlock *B = cast_or_null<BasicBlock>(*I); + Dom = B ? DT->findNearestCommonDominator(Dom, B) : nullptr; + if (!Dom) return nullptr; - BasicBlock *Dom = cast<BasicBlock>(*I); - while (++I != E) { - BasicBlock *B = cast_or_null<BasicBlock>(*I); - Dom = B ? DT->findNearestCommonDominator(Dom, B) : nullptr; - if (!Dom) - return nullptr; } - DEBUG(dbgs() << "computed:" << Dom->getName() << '\n'); + LLVM_DEBUG(dbgs() << "computed:" << Dom->getName() << '\n'); return Dom; } @@ -753,7 +753,7 @@ static bool is_empty(const BasicBlock *B) { BasicBlock *HexagonCommonGEP::recalculatePlacement(GepNode *Node, NodeChildrenMap &NCM, NodeToValueMap &Loc) { - DEBUG(dbgs() << "Loc for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "Loc for node:" << Node << '\n'); // Recalculate the placement for Node, assuming that the locations of // its children in Loc are valid. // Return nullptr if there is no valid placement for Node (for example, it @@ -820,7 +820,7 @@ BasicBlock *HexagonCommonGEP::recalculatePlacement(GepNode *Node, BasicBlock *HexagonCommonGEP::recalculatePlacementRec(GepNode *Node, NodeChildrenMap &NCM, NodeToValueMap &Loc) { - DEBUG(dbgs() << "LocRec begin for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "LocRec begin for node:" << Node << '\n'); // Recalculate the placement of Node, after recursively recalculating the // placements of all its children. NodeChildrenMap::iterator CF = NCM.find(Node); @@ -830,7 +830,7 @@ BasicBlock *HexagonCommonGEP::recalculatePlacementRec(GepNode *Node, recalculatePlacementRec(*I, NCM, Loc); } BasicBlock *LB = recalculatePlacement(Node, NCM, Loc); - DEBUG(dbgs() << "LocRec end for node:" << Node << '\n'); + LLVM_DEBUG(dbgs() << "LocRec end for node:" << Node << '\n'); return LB; } @@ -952,8 +952,8 @@ namespace { void HexagonCommonGEP::separateChainForNode(GepNode *Node, Use *U, NodeToValueMap &Loc) { User *R = U->getUser(); - DEBUG(dbgs() << "Separating chain for node (" << Node << ") user: " - << *R << '\n'); + LLVM_DEBUG(dbgs() << "Separating chain for node (" << Node << ") user: " << *R + << '\n'); BasicBlock *PB = cast<Instruction>(R)->getParent(); GepNode *N = Node; @@ -996,7 +996,7 @@ void HexagonCommonGEP::separateChainForNode(GepNode *Node, Use *U, // Should at least have U in NewUs. NewNode->Flags |= GepNode::Used; - DEBUG(dbgs() << "new node: " << NewNode << " " << *NewNode << '\n'); + LLVM_DEBUG(dbgs() << "new node: " << NewNode << " " << *NewNode << '\n'); assert(!NewUs.empty()); Uses[NewNode] = NewUs; } @@ -1007,7 +1007,7 @@ void HexagonCommonGEP::separateConstantChains(GepNode *Node, NodeSet Ns; nodes_for_root(Node, NCM, Ns); - DEBUG(dbgs() << "Separating constant chains for node: " << Node << '\n'); + LLVM_DEBUG(dbgs() << "Separating constant chains for node: " << Node << '\n'); // Collect all used nodes together with the uses from loads and stores, // where the GEP node could be folded into the load/store instruction. NodeToUsesMap FNs; // Foldable nodes. @@ -1044,7 +1044,7 @@ void HexagonCommonGEP::separateConstantChains(GepNode *Node, FNs.insert(std::make_pair(N, LSs)); } - DEBUG(dbgs() << "Nodes with foldable users:\n" << FNs); + LLVM_DEBUG(dbgs() << "Nodes with foldable users:\n" << FNs); for (NodeToUsesMap::iterator I = FNs.begin(), E = FNs.end(); I != E; ++I) { GepNode *N = I->first; @@ -1066,32 +1066,33 @@ void HexagonCommonGEP::computeNodePlacement(NodeToValueMap &Loc) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) recalculatePlacementRec(*I, NCM, Loc); - DEBUG(dbgs() << "Initial node placement:\n" << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Initial node placement:\n" << LocationAsBlock(Loc)); if (OptEnableInv) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) adjustForInvariance(*I, NCM, Loc); - DEBUG(dbgs() << "Node placement after adjustment for invariance:\n" - << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Node placement after adjustment for invariance:\n" + << LocationAsBlock(Loc)); } if (OptEnableConst) { for (NodeVect::iterator I = Roots.begin(), E = Roots.end(); I != E; ++I) separateConstantChains(*I, NCM, Loc); } - DEBUG(dbgs() << "Node use information:\n" << Uses); + LLVM_DEBUG(dbgs() << "Node use information:\n" << Uses); // At the moment, there is no further refinement of the initial placement. // Such a refinement could include splitting the nodes if they are placed // too far from some of its users. - DEBUG(dbgs() << "Final node placement:\n" << LocationAsBlock(Loc)); + LLVM_DEBUG(dbgs() << "Final node placement:\n" << LocationAsBlock(Loc)); } Value *HexagonCommonGEP::fabricateGEP(NodeVect &NA, BasicBlock::iterator At, BasicBlock *LocB) { - DEBUG(dbgs() << "Fabricating GEP in " << LocB->getName() - << " for nodes:\n" << NA); + LLVM_DEBUG(dbgs() << "Fabricating GEP in " << LocB->getName() + << " for nodes:\n" + << NA); unsigned Num = NA.size(); GepNode *RN = NA[0]; assert((RN->Flags & GepNode::Root) && "Creating GEP for non-root"); @@ -1128,7 +1129,7 @@ Value *HexagonCommonGEP::fabricateGEP(NodeVect &NA, BasicBlock::iterator At, Type *ElTy = cast<PointerType>(InpTy->getScalarType())->getElementType(); NewInst = GetElementPtrInst::Create(ElTy, Input, A, "cgep", &*At); NewInst->setIsInBounds(RN->Flags & GepNode::InBounds); - DEBUG(dbgs() << "new GEP: " << *NewInst << '\n'); + LLVM_DEBUG(dbgs() << "new GEP: " << *NewInst << '\n'); Input = NewInst; } while (nax <= Num); @@ -1161,7 +1162,7 @@ void HexagonCommonGEP::getAllUsersForNode(GepNode *Node, ValueVect &Values, } void HexagonCommonGEP::materialize(NodeToValueMap &Loc) { - DEBUG(dbgs() << "Nodes before materialization:\n" << Nodes << '\n'); + LLVM_DEBUG(dbgs() << "Nodes before materialization:\n" << Nodes << '\n'); NodeChildrenMap NCM; NodeVect Roots; // Compute the inversion again, since computing placement could alter diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index a2adc43bc48..8b024fad4f8 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1258,7 +1258,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, if (!ED.IsDef) continue; ExtValue EV(ED); - DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n'); + LLVM_DEBUG(dbgs() << " =" << I << ". " << EV << " " << ED << '\n'); assert(ED.Rd.Reg != 0); Ranges[I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset); // A2_tfrsi is a special case: it will be replaced with A2_addi, which @@ -1278,7 +1278,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, if (ED.IsDef) continue; ExtValue EV(ED); - DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n'); + LLVM_DEBUG(dbgs() << " " << I << ". " << EV << " " << ED << '\n'); OffsetRange Dev = getOffsetRange(ED); Ranges[I-Begin].intersect(Dev.shift(EV.Offset)); } @@ -1290,7 +1290,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, for (unsigned I = Begin; I != End; ++I) RangeMap[Ranges[I-Begin]].insert(I); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Ranges\n"; for (unsigned I = Begin; I != End; ++I) dbgs() << " " << I << ". " << Ranges[I-Begin] << '\n'; @@ -1384,7 +1384,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, } } - DEBUG(dbgs() << "IMap (before fixup) = " << PrintIMap(IMap, *HRI)); + LLVM_DEBUG(dbgs() << "IMap (before fixup) = " << PrintIMap(IMap, *HRI)); // There is some ambiguity in what initializer should be used, if the // descriptor's subexpression is non-trivial: it can be the entire @@ -1454,7 +1454,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, } } - DEBUG(dbgs() << "IMap (after fixup) = " << PrintIMap(IMap, *HRI)); + LLVM_DEBUG(dbgs() << "IMap (after fixup) = " << PrintIMap(IMap, *HRI)); } void HCE::calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs, @@ -1557,9 +1557,9 @@ HCE::Register HCE::insertInitializer(Loc DefL, const ExtenderInit &ExtI) { assert(InitI); (void)InitI; - DEBUG(dbgs() << "Inserted def in bb#" << MBB.getNumber() - << " for initializer: " << PrintInit(ExtI, *HRI) - << "\n " << *InitI); + LLVM_DEBUG(dbgs() << "Inserted def in bb#" << MBB.getNumber() + << " for initializer: " << PrintInit(ExtI, *HRI) << "\n " + << *InitI); return { DefR, 0 }; } @@ -1812,8 +1812,8 @@ bool HCE::replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI) { ExtValue EV(ED); int32_t Diff = EV.Offset - DefV.Offset; const MachineInstr &MI = *ED.UseMI; - DEBUG(dbgs() << __func__ << " Idx:" << Idx << " ExtR:" - << PrintRegister(ExtR, *HRI) << " Diff:" << Diff << '\n'); + LLVM_DEBUG(dbgs() << __func__ << " Idx:" << Idx << " ExtR:" + << PrintRegister(ExtR, *HRI) << " Diff:" << Diff << '\n'); // These two addressing modes must be converted into indexed forms // regardless of what the initializer looks like. @@ -1919,7 +1919,7 @@ const MachineOperand &HCE::getStoredValueOp(const MachineInstr &MI) const { bool HCE::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr)); + LLVM_DEBUG(MF.print(dbgs() << "Before " << getPassName() << '\n', nullptr)); HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); @@ -1934,7 +1934,7 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { }); bool Changed = false; - DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n"); + LLVM_DEBUG(dbgs() << "Collected " << Extenders.size() << " extenders\n"); for (unsigned I = 0, E = Extenders.size(); I != E; ) { unsigned B = I; const ExtRoot &T = Extenders[B].getOp(); @@ -1946,7 +1946,7 @@ bool HCE::runOnMachineFunction(MachineFunction &MF) { Changed |= replaceExtenders(IMap); } - DEBUG({ + LLVM_DEBUG({ if (Changed) MF.print(dbgs() << "After " << getPassName() << '\n', nullptr); else diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 730cfafae42..8f22a71dc1f 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -617,7 +617,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os, void MachineConstPropagator::visitPHI(const MachineInstr &PN) { const MachineBasicBlock *MB = PN.getParent(); unsigned MBN = MB->getNumber(); - DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); + LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); const MachineOperand &MD = PN.getOperand(0); Register DefR(MD); @@ -642,8 +642,8 @@ Bottomize: const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB(); unsigned PBN = PB->getNumber(); if (!EdgeExec.count(CFGEdge(PBN, MBN))) { - DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" - << printMBBReference(*MB) << " not executable\n"); + LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" + << printMBBReference(*MB) << " not executable\n"); continue; } const MachineOperand &SO = PN.getOperand(i); @@ -658,8 +658,9 @@ Bottomize: LatticeCell SrcC; bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); - DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": " - << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n'); + LLVM_DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": " + << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC + << '\n'); Changed |= Eval ? DefC.meet(SrcC) : DefC.setBottom(); Cells.update(DefR.Reg, DefC); @@ -671,11 +672,11 @@ Bottomize: } void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) { - DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent()) - << "): " << MI); + LLVM_DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent()) + << "): " << MI); CellMap Outputs; bool Eval = MCE.evaluate(MI, Cells, Outputs); - DEBUG({ + LLVM_DEBUG({ if (Eval) { dbgs() << " outputs:"; for (auto &I : Outputs) @@ -728,8 +729,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { while (It != End) { const MachineInstr &MI = *It; InstrExec.insert(&MI); - DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(" - << printMBBReference(B) << "): " << MI); + LLVM_DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(" + << printMBBReference(B) << "): " << MI); // Do not evaluate subsequent branches if the evaluation of any of the // previous branches failed. Keep iterating over the branches only // to mark them as executable. @@ -763,23 +764,23 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { // last one set "FallsThru", then add an edge to the layout successor // to the targets. Targets.clear(); - DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG " - "successors\n"); + LLVM_DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG " + "successors\n"); for (const MachineBasicBlock *SB : B.successors()) Targets.insert(SB); } for (const MachineBasicBlock *TB : Targets) { unsigned TBN = TB->getNumber(); - DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " - << printMBBReference(*TB) << "\n"); + LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " + << printMBBReference(*TB) << "\n"); FlowQ.push(CFGEdge(MBN, TBN)); } } void MachineConstPropagator::visitUsesOf(unsigned Reg) { - DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) - << Cells.get(Reg) << '\n'); + LLVM_DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI) + << Cells.get(Reg) << '\n'); for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) { // Do not process non-executable instructions. They can become exceutable // later (via a flow-edge in the work queue). In such case, the instruc- @@ -870,10 +871,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); - DEBUG(dbgs() << "Picked edge " - << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" - << printMBBReference(*MF.getBlockNumbered(Edge.second)) - << '\n'); + LLVM_DEBUG( + dbgs() << "Picked edge " + << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" + << printMBBReference(*MF.getBlockNumbered(Edge.second)) << '\n'); if (Edge.first != EntryNum) if (EdgeExec.count(Edge)) continue; @@ -927,7 +928,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { } } // while (FlowQ) - DEBUG({ + LLVM_DEBUG({ dbgs() << "Cells after propagation:\n"; Cells.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n"; @@ -1042,7 +1043,7 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) { // This is the constant propagation algorithm as described by Wegman-Zadeck. // Most of the terminology comes from there. bool MachineConstPropagator::run(MachineFunction &MF) { - DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr)); + LLVM_DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr)); MRI = &MF.getRegInfo(); @@ -1054,7 +1055,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) { propagate(MF); bool Changed = rewrite(MF); - DEBUG({ + LLVM_DEBUG({ dbgs() << "End of MachineConstPropagator (Changed=" << Changed << ")\n"; if (Changed) MF.print(dbgs(), nullptr); @@ -2778,7 +2779,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, AllDefs = false; // Some diagnostics. - // DEBUG({...}) gets confused with all this code as an argument. + // LLVM_DEBUG({...}) gets confused with all this code as an argument. #ifndef NDEBUG bool Debugging = DebugFlag && isCurrentDebugType(DEBUG_TYPE); if (Debugging) { @@ -2923,7 +2924,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI, ChangedNum++; } - DEBUG({ + LLVM_DEBUG({ if (!NewInstrs.empty()) { MachineFunction &MF = *MI.getParent()->getParent(); dbgs() << "In function: " << MF.getName() << "\n"; @@ -3090,7 +3091,7 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI, MO.setIsKill(false); } - DEBUG({ + LLVM_DEBUG({ if (NewMI) { dbgs() << "Rewrite: for " << MI; if (NewMI != &MI) @@ -3130,7 +3131,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, if (BrI.getOpcode() == Hexagon::J2_jump) return false; - DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI); + LLVM_DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI); bool Rewritten = false; if (NumTargets > 0) { assert(!FallsThru && "This should have been checked before"); diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index f3d24739da4..fccde96d8a3 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -649,7 +649,7 @@ void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt, unsigned DoubleDestReg, MachineOperand &HiOperand, MachineOperand &LoOperand) { - DEBUG(dbgs() << "Found a CONST64\n"); + LLVM_DEBUG(dbgs() << "Found a CONST64\n"); DebugLoc DL = InsertPt->getDebugLoc(); MachineBasicBlock *BB = InsertPt->getParent(); diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index bbd06ff747e..557e6384be6 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -238,7 +238,8 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const { bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) { - DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n"); + LLVM_DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) + << "\n"); // Interested only in conditional branches, no .new, no new-value, etc. // Check the terminators directly, it's easier than handling all responses @@ -325,13 +326,13 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, } // Don't try to predicate loop preheaders. if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) { - DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB) - << " is a loop preheader. Skipping.\n"); + LLVM_DEBUG(dbgs() << "One of blocks " << PrintMB(TB) << ", " << PrintMB(FB) + << " is a loop preheader. Skipping.\n"); return false; } FP = FlowPattern(B, PredR, TB, FB, JB); - DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n"); + LLVM_DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n"); return true; } @@ -551,8 +552,9 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { }; unsigned Spare = 0; unsigned TotalIn = TotalCount(FP.TrueB, Spare) + TotalCount(FP.FalseB, Spare); - DEBUG(dbgs() << "Total number of instructions to be predicated/speculated: " - << TotalIn << ", spare room: " << Spare << "\n"); + LLVM_DEBUG( + dbgs() << "Total number of instructions to be predicated/speculated: " + << TotalIn << ", spare room: " << Spare << "\n"); if (TotalIn >= SizeLimit+Spare) return false; @@ -579,12 +581,13 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { PredDefs += countPredicateDefs(SB); } } - DEBUG(dbgs() << "Total number of extra muxes from converted phis: " - << TotalPh << "\n"); + LLVM_DEBUG(dbgs() << "Total number of extra muxes from converted phis: " + << TotalPh << "\n"); if (TotalIn+TotalPh >= SizeLimit+Spare) return false; - DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n"); + LLVM_DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs + << "\n"); if (PredDefs > 4) return false; @@ -625,11 +628,11 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, return Changed; if (!isValid(FP)) { - DEBUG(dbgs() << "Conversion is not valid\n"); + LLVM_DEBUG(dbgs() << "Conversion is not valid\n"); return Changed; } if (!isProfitable(FP)) { - DEBUG(dbgs() << "Conversion is not profitable\n"); + LLVM_DEBUG(dbgs() << "Conversion is not profitable\n"); return Changed; } @@ -640,8 +643,9 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B, bool HexagonEarlyIfConversion::visitLoop(MachineLoop *L) { MachineBasicBlock *HB = L ? L->getHeader() : nullptr; - DEBUG((L ? dbgs() << "Visiting loop H:" << PrintMB(HB) - : dbgs() << "Visiting function") << "\n"); + LLVM_DEBUG((L ? dbgs() << "Visiting loop H:" << PrintMB(HB) + : dbgs() << "Visiting function") + << "\n"); bool Changed = false; if (L) { for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) @@ -758,7 +762,7 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB, void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB, MachineBasicBlock::iterator At, MachineBasicBlock *FromB, unsigned PredR, bool IfTrue) { - DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n"); + LLVM_DEBUG(dbgs() << "Predicating block " << PrintMB(FromB) << "\n"); MachineBasicBlock::iterator End = FromB->getFirstTerminator(); MachineBasicBlock::iterator I, NextI; @@ -950,7 +954,7 @@ void HexagonEarlyIfConversion::convert(const FlowPattern &FP) { } void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) { - DEBUG(dbgs() << "Removing block " << PrintMB(B) << "\n"); + LLVM_DEBUG(dbgs() << "Removing block " << PrintMB(B) << "\n"); // Transfer the immediate dominator information from B to its descendants. MachineDomTreeNode *N = MDT->getNode(B); @@ -980,7 +984,7 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) { } void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) { - DEBUG(dbgs() << "Removing phi nodes from block " << PrintMB(B) << "\n"); + LLVM_DEBUG(dbgs() << "Removing phi nodes from block " << PrintMB(B) << "\n"); MachineBasicBlock::iterator I, NextI, NonPHI = B->getFirstNonPHI(); for (I = B->begin(); I != NonPHI; I = NextI) { NextI = std::next(I); @@ -1007,8 +1011,8 @@ void HexagonEarlyIfConversion::eliminatePhis(MachineBasicBlock *B) { void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB, MachineBasicBlock *SuccB) { - DEBUG(dbgs() << "Merging blocks " << PrintMB(PredB) << " and " - << PrintMB(SuccB) << "\n"); + LLVM_DEBUG(dbgs() << "Merging blocks " << PrintMB(PredB) << " and " + << PrintMB(SuccB) << "\n"); bool TermOk = hasUncondBranch(SuccB); eliminatePhis(SuccB); HII->removeBranch(*PredB); diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 06caa2feffa..d3222a63ead 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -650,7 +650,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, .add(SrcOp); } - DEBUG(dbgs() << "created an initial copy: " << *MIB); + LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB); return &*MIB; } @@ -663,8 +663,8 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, return false; TfrCounter++; } - DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": " - << MI); + LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) + << ": " << MI); MachineOperand &MD = MI.getOperand(0); // Definition MachineOperand &MP = MI.getOperand(1); // Predicate register assert(MD.isDef()); @@ -941,8 +941,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, unsigned Opc = TfrI.getOpcode(); (void)Opc; assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf); - DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") - << ": " << TfrI); + LLVM_DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") + << ": " << TfrI); MachineOperand &MD = TfrI.getOperand(0); MachineOperand &MP = TfrI.getOperand(1); @@ -963,7 +963,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, if (!DefI || !isPredicable(DefI)) return false; - DEBUG(dbgs() << "Source def: " << *DefI); + LLVM_DEBUG(dbgs() << "Source def: " << *DefI); // Collect the information about registers defined and used between the // DefI and the TfrI. @@ -1048,8 +1048,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, if (!canMoveMemTo(*DefI, TfrI, true)) CanDown = false; - DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") - << ", can move down: " << (CanDown ? "yes\n" : "no\n")); + LLVM_DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") + << ", can move down: " << (CanDown ? "yes\n" : "no\n")); MachineBasicBlock::iterator PastDefIt = std::next(DefIt); if (CanUp) predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs); @@ -1144,10 +1144,10 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { return false; bool Overlap = L1.overlaps(L2); - DEBUG(dbgs() << "compatible registers: (" - << (Overlap ? "overlap" : "disjoint") << ")\n " - << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " - << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); + LLVM_DEBUG(dbgs() << "compatible registers: (" + << (Overlap ? "overlap" : "disjoint") << ")\n " + << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " + << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); if (R1.Sub || R2.Sub) return false; if (Overlap) @@ -1180,7 +1180,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { LIS->removeInterval(R2.Reg); updateKillFlags(R1.Reg); - DEBUG(dbgs() << "coalesced: " << L1 << "\n"); + LLVM_DEBUG(dbgs() << "coalesced: " << L1 << "\n"); L1.verify(); return true; @@ -1261,8 +1261,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { LIS = &getAnalysis<LiveIntervals>(); MRI = &MF.getRegInfo(); - DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", - MF.getFunction().getParent())); + LLVM_DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", + MF.getFunction().getParent())); bool Changed = false; std::set<unsigned> CoalUpd, PredUpd; @@ -1289,8 +1289,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { if (!CoalUpd.count(Op.getReg())) KillUpd.insert(Op.getReg()); updateLiveness(KillUpd, false, true, false); - DEBUG(LIS->print(dbgs() << "After coalescing\n", - MF.getFunction().getParent())); + LLVM_DEBUG( + LIS->print(dbgs() << "After coalescing\n", MF.getFunction().getParent())); // First, simply split all muxes into a pair of conditional transfers // and update the live intervals to reflect the new arrangement. The @@ -1306,8 +1306,8 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { // predication, and after splitting they are difficult to recalculate // (because of predicated defs), so make sure they are left untouched. // Predication does not use live intervals. - DEBUG(LIS->print(dbgs() << "After splitting\n", - MF.getFunction().getParent())); + LLVM_DEBUG( + LIS->print(dbgs() << "After splitting\n", MF.getFunction().getParent())); // Traverse all blocks and collapse predicable instructions feeding // conditional transfers into predicated instructions. @@ -1315,13 +1315,13 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { // cases that were not created in the previous step. for (auto &B : MF) Changed |= predicateInBlock(B, PredUpd); - DEBUG(LIS->print(dbgs() << "After predicating\n", - MF.getFunction().getParent())); + LLVM_DEBUG(LIS->print(dbgs() << "After predicating\n", + MF.getFunction().getParent())); PredUpd.insert(CoalUpd.begin(), CoalUpd.end()); updateLiveness(PredUpd, true, true, true); - DEBUG({ + LLVM_DEBUG({ if (Changed) LIS->print(dbgs() << "After expand-condsets\n", MF.getFunction().getParent()); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 4b3e11ed3fd..97b02e2b34c 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -442,7 +442,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, if (needsStackFrame(I, CSR, HRI)) SFBlocks.push_back(&I); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Blocks needing SF: {"; for (auto &B : SFBlocks) dbgs() << " " << printMBBReference(*B); @@ -465,7 +465,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, if (!PDomB) break; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Computed dom block: "; if (DomB) dbgs() << printMBBReference(*DomB); @@ -483,11 +483,11 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, // Make sure that DomB dominates PDomB and PDomB post-dominates DomB. if (!MDT.dominates(DomB, PDomB)) { - DEBUG(dbgs() << "Dom block does not dominate pdom block\n"); + LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n"); return; } if (!MPT.dominates(PDomB, DomB)) { - DEBUG(dbgs() << "PDom block does not post-dominate dom block\n"); + LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n"); return; } @@ -1396,7 +1396,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const { - DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n'); MachineFrameInfo &MFI = MF.getFrameInfo(); BitVector SRegs(Hexagon::NUM_TARGET_REGS); @@ -1406,15 +1406,16 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, // (1) For each callee-saved register, add that register and all of its // sub-registers to SRegs. - DEBUG(dbgs() << "Initial CS registers: {"); + LLVM_DEBUG(dbgs() << "Initial CS registers: {"); for (unsigned i = 0, n = CSI.size(); i < n; ++i) { unsigned R = CSI[i].getReg(); - DEBUG(dbgs() << ' ' << printReg(R, TRI)); + LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI)); for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = true; } - DEBUG(dbgs() << " }\n"); - DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << " }\n"); + LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (2) For each reserved register, remove that register and all of its // sub- and super-registers from SRegs. @@ -1424,8 +1425,10 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR) SRegs[*SR] = false; } - DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); dbgs() << "\n"); - DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI); + dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (3) Collect all registers that have at least one sub-register in SRegs, // and also have no sub-registers that are reserved. These will be the can- @@ -1446,11 +1449,13 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, break; } } - DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI); + dbgs() << "\n"); // (4) Include all super-registers found in (3) into SRegs. SRegs |= TmpSup; - DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // (5) For each register R in SRegs, if any super-register of R is in SRegs, // remove R from SRegs. @@ -1463,7 +1468,8 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, break; } } - DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI); + dbgs() << "\n"); // Now, for each register that has a fixed stack slot, create the stack // object for it. @@ -1501,7 +1507,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, SRegs[R] = false; } - DEBUG({ + LLVM_DEBUG({ dbgs() << "CS information: {"; for (unsigned i = 0, n = CSI.size(); i < n; ++i) { int FI = CSI[i].getFrameIdx(); @@ -2021,8 +2027,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto P = BlockIndexes.insert( std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B))); auto &IndexMap = P.first->second; - DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n" - << IndexMap << '\n'); + LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n" + << IndexMap << '\n'); for (auto &In : B) { int LFI, SFI; @@ -2129,7 +2135,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } } - DEBUG({ + LLVM_DEBUG({ for (auto &P : FIRangeMap) { dbgs() << "fi#" << P.first; if (BadFIs.count(P.first)) @@ -2168,7 +2174,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, } } - DEBUG({ + LLVM_DEBUG({ dbgs() << "Block-to-FI map (* -- live-on-exit):\n"; for (auto &P : BlockFIMap) { auto &FIs = P.second; @@ -2195,16 +2201,16 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, HexagonBlockRanges::InstrIndexMap &IM = F->second; HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM); HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM); - DEBUG(dbgs() << printMBBReference(B) << " dead map\n" - << HexagonBlockRanges::PrintRangeMap(DM, HRI)); + LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n" + << HexagonBlockRanges::PrintRangeMap(DM, HRI)); for (auto FI : BlockFIMap[&B]) { if (BadFIs.count(FI)) continue; - DEBUG(dbgs() << "Working on fi#" << FI << '\n'); + LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n'); HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; for (auto &Range : RL) { - DEBUG(dbgs() << "--Examining range:" << RL << '\n'); + LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n'); if (!IndexType::isInstr(Range.start()) || !IndexType::isInstr(Range.end())) continue; @@ -2219,7 +2225,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); // The this-> is needed to unconfuse MSVC. unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC); - DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n'); + LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) + << '\n'); if (FoundR == 0) continue; #ifndef NDEBUG diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index 9288ed03d4d..c0d2de90467 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -222,13 +222,12 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { } void HexagonGenPredicate::processPredicateGPR(const Register &Reg) { - DEBUG(dbgs() << __func__ << ": " - << printReg(Reg.R, TRI, Reg.S) << "\n"); + LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); using use_iterator = MachineRegisterInfo::use_iterator; use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); if (I == E) { - DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); + LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); MachineInstr *DefI = MRI->getVRegDef(Reg.R); DefI->eraseFromParent(); return; @@ -250,7 +249,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { if (F != G2P.end()) return F->second; - DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI)); + LLVM_DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI)); MachineInstr *DefI = MRI->getVRegDef(Reg.R); assert(DefI); unsigned Opc = DefI->getOpcode(); @@ -258,7 +257,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); Register PR = DefI->getOperand(1); G2P.insert(std::make_pair(Reg, PR)); - DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); + LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); return PR; } @@ -274,7 +273,8 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) { BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) .addReg(Reg.R, 0, Reg.S); G2P.insert(std::make_pair(Reg, Register(NewPR))); - DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) << '\n'); + LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) + << '\n'); return Register(NewPR); } @@ -364,7 +364,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { } bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { - DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI); + LLVM_DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI); unsigned Opc = MI->getOpcode(); assert(isConvertibleToPredForm(MI)); @@ -426,7 +426,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { Register Pred = getPredRegFor(GPR); MIB.addReg(Pred.R, 0, Pred.S); } - DEBUG(dbgs() << "generated: " << *MIB); + LLVM_DEBUG(dbgs() << "generated: " << *MIB); // Generate a copy-out: NewGPR = NewPR, and replace all uses of OutR // with NewGPR. @@ -449,7 +449,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { } bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { - DEBUG(dbgs() << __func__ << "\n"); + LLVM_DEBUG(dbgs() << __func__ << "\n"); const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; bool Changed = false; VectOfInst Erase; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index e3d5825b269..0e33976a58a 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -376,7 +376,7 @@ FunctionPass *llvm::createHexagonHardwareLoops() { } bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n"); + LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n"); if (skipFunction(MF.getFunction())) return false; @@ -1012,14 +1012,15 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const { const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); + LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) { const MachineInstr *MI = &*MII; if (isInvalidLoopOperation(MI, IsInnerHWLoop)) { - DEBUG(dbgs()<< "\nCannot convert to hw_loop due to:"; MI->dump();); + LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:"; + MI->dump();); return true; } } @@ -1084,7 +1085,7 @@ void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) { SmallVector<MachineInstr*, 1> DeadPhis; if (isDead(MI, DeadPhis)) { - DEBUG(dbgs() << "HW looping will remove: " << *MI); + LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI); // It is possible that some DBG_VALUE instructions refer to this // instruction. Examine each def operand for such references; @@ -1238,7 +1239,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L, LoopStart = TopBlock; // Convert the loop to a hardware loop. - DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); + LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); DebugLoc DL; if (InsertPos != Preheader->end()) DL = InsertPos->getDebugLoc(); @@ -1368,7 +1369,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, LoopFeederMap &LoopFeederPhi) const { if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) { const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); + LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); // Ignore all BBs that form Loop. for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; @@ -1769,16 +1770,16 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) { MachineOperand &MO = PredDef->getOperand(i); if (MO.isReg() && MO.getReg() == RB.first) { - DEBUG(dbgs() << "\n DefMI(" << i << ") = " - << *(MRI->getVRegDef(I->first))); + LLVM_DEBUG(dbgs() << "\n DefMI(" << i + << ") = " << *(MRI->getVRegDef(I->first))); if (IndI) return false; IndI = MRI->getVRegDef(I->first); IndMO = &MO; } else if (MO.isReg()) { - DEBUG(dbgs() << "\n DefMI(" << i << ") = " - << *(MRI->getVRegDef(MO.getReg()))); + LLVM_DEBUG(dbgs() << "\n DefMI(" << i + << ") = " << *(MRI->getVRegDef(MO.getReg()))); if (nonIndI) return false; diff --git a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp index 8ac333f4f01..44f1f554c66 100644 --- a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define DEBUG_TYPE "post-RA-sched" void HexagonHazardRecognizer::Reset() { - DEBUG(dbgs() << "Reset hazard recognizer\n"); + LLVM_DEBUG(dbgs() << "Reset hazard recognizer\n"); Resources->clearResources(); PacketNum = 0; UsesDotCur = nullptr; @@ -43,7 +43,7 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { return NoHazard; if (!Resources->canReserveResources(*MI)) { - DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI); + LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI); HazardType RetVal = Hazard; if (TII->mayBeNewStore(*MI)) { // Make sure the register to be stored is defined by an instruction in the @@ -59,14 +59,16 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { MI->getDebugLoc()); if (Resources->canReserveResources(*NewMI)) RetVal = NoHazard; - DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) << "\n"); + LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) + << "\n"); MF->DeleteMachineInstr(NewMI); } return RetVal; } if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) { - DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " << *MI); + LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " + << *MI); return Hazard; } @@ -74,7 +76,7 @@ HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { } void HexagonHazardRecognizer::AdvanceCycle() { - DEBUG(dbgs() << "Advance cycle, clear state\n"); + LLVM_DEBUG(dbgs() << "Advance cycle, clear state\n"); Resources->clearResources(); if (DotCurPNum != -1 && DotCurPNum != (int)PacketNum) { UsesDotCur = nullptr; @@ -132,7 +134,7 @@ void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { } else Resources->reserveResources(*MI); - DEBUG(dbgs() << " Add instruction " << *MI); + LLVM_DEBUG(dbgs() << " Add instruction " << *MI); // When scheduling a dot cur instruction, check if there is an instruction // that can use the dot cur in the same packet. If so, we'll attempt to diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index e639d13bd2b..20e8dcdb06f 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1892,15 +1892,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { RootHeights[N] = std::max(getHeight(N->getOperand(0).getNode()), getHeight(N->getOperand(1).getNode())) + 1; - DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight - << " Height=" << RootHeights[N] << "): "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight + << " Height=" << RootHeights[N] << "): "); + LLVM_DEBUG(N->dump(CurDAG)); return SDValue(N, 0); } - DEBUG(dbgs() << "** Balancing root node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "** Balancing root node: "); + LLVM_DEBUG(N->dump(CurDAG)); unsigned NOpcode = N->getOpcode(); @@ -1948,7 +1948,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // Whoops, this node was RAUWd by one of the balanceSubTree calls we // made. Our worklist isn't up to date anymore. // Restart the whole process. - DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); + LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); return balanceSubTree(N, TopLevel); } @@ -2019,15 +2019,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } } - DEBUG(dbgs() << "--> Current height=" << NodeHeights[SDValue(N, 0)] - << " weight=" << CurrentWeight << " imbalanced=" - << Imbalanced << "\n"); + LLVM_DEBUG(dbgs() << "--> Current height=" << NodeHeights[SDValue(N, 0)] + << " weight=" << CurrentWeight + << " imbalanced=" << Imbalanced << "\n"); // Transform MUL(x, C * 2^Y) + SHL(z, Y) -> SHL(ADD(MUL(x, C), z), Y) // This factors out a shift in order to match memw(a<<Y+b). if (CanFactorize && (willShiftRightEliminate(Mul1.Value, MaxPowerOf2) || willShiftRightEliminate(Mul2.Value, MaxPowerOf2))) { - DEBUG(dbgs() << "--> Found common factor for two MUL children!\n"); + LLVM_DEBUG(dbgs() << "--> Found common factor for two MUL children!\n"); int Weight = Mul1.Weight + Mul2.Weight; int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1; SDValue Mul1Factored = factorOutPowerOf2(Mul1.Value, MaxPowerOf2); @@ -2061,9 +2061,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { if (getUsesInFunction(GANode->getGlobal()) == 1 && Offset->hasOneUse() && getTargetLowering()->isOffsetFoldingLegal(GANode)) { - DEBUG(dbgs() << "--> Combining GA and offset (" << Offset->getSExtValue() - << "): "); - DEBUG(GANode->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> Combining GA and offset (" + << Offset->getSExtValue() << "): "); + LLVM_DEBUG(GANode->dump(CurDAG)); SDValue NewTGA = CurDAG->getTargetGlobalAddress(GANode->getGlobal(), SDLoc(GA.Value), @@ -2107,7 +2107,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // If this is the top level and we haven't factored out a shift, we should try // to move a constant to the bottom to match addressing modes like memw(rX+C) if (TopLevel && !CanFactorize && Leaves.hasConst()) { - DEBUG(dbgs() << "--> Pushing constant to tip of tree."); + LLVM_DEBUG(dbgs() << "--> Pushing constant to tip of tree."); Leaves.pushToBottom(Leaves.pop()); } @@ -2134,7 +2134,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // Make sure that none of these nodes have been RAUW'd if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || (RootWeights.count(V1.getNode()) && RootWeights[V1.getNode()] == -2)) { - DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); + LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n"); return balanceSubTree(N, TopLevel); } @@ -2168,9 +2168,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { int Weight = V0Weight + V1Weight; Leaves.push(WeightedLeaf(NewNode, Weight, L0.InsertionOrder)); - DEBUG(dbgs() << "--> Built new node (Weight=" << Weight << ",Height=" - << Height << "):\n"); - DEBUG(NewNode.dump()); + LLVM_DEBUG(dbgs() << "--> Built new node (Weight=" << Weight + << ",Height=" << Height << "):\n"); + LLVM_DEBUG(NewNode.dump()); } assert(Leaves.size() == 1); @@ -2194,15 +2194,15 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } if (N != NewRoot.getNode()) { - DEBUG(dbgs() << "--> Root is now: "); - DEBUG(NewRoot.dump()); + LLVM_DEBUG(dbgs() << "--> Root is now: "); + LLVM_DEBUG(NewRoot.dump()); // Replace all uses of old root by new root CurDAG->ReplaceAllUsesWith(N, NewRoot.getNode()); // Mark that we have RAUW'd N RootWeights[N] = -2; } else { - DEBUG(dbgs() << "--> Root unchanged.\n"); + LLVM_DEBUG(dbgs() << "--> Root unchanged.\n"); } RootWeights[NewRoot.getNode()] = Leaves.top().Weight; @@ -2225,8 +2225,8 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { if (RootWeights.count(BasePtr.getNode())) continue; - DEBUG(dbgs() << "** Rebalancing address calculation in node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "** Rebalancing address calculation in node: "); + LLVM_DEBUG(N->dump(CurDAG)); // FindRoots SmallVector<SDNode *, 4> Worklist; @@ -2266,8 +2266,8 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), NewBasePtr, N->getOperand(3)); - DEBUG(dbgs() << "--> Final node: "); - DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "--> Final node: "); + LLVM_DEBUG(N->dump(CurDAG)); } CurDAG->RemoveDeadNodes(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index be036b3ddb3..fbe8f16bd98 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -359,9 +359,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, break; } } - DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n" - : "Argument must be passed on stack. " - "Not eligible for Tail Call\n")); + LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n" + : "Argument must be passed on stack. " + "Not eligible for Tail Call\n")); } // Get a count of how many bytes are to be pushed on the stack. unsigned NumBytes = CCInfo.getNextStackOffset(); @@ -433,7 +433,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } if (NeedsArgAlign && Subtarget.hasV60TOps()) { - DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); + LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); LargestAlignSeen = std::max(LargestAlignSeen, VecAlign); MFI.ensureMaxAlignment(LargestAlignSeen); @@ -670,7 +670,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, if (A == 0) A = HFI.getStackAlignment(); - DEBUG({ + LLVM_DEBUG({ dbgs () << __func__ << " Align: " << A << " Size: "; Size.getNode()->dump(&DAG); dbgs() << "\n"; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1ec1ce01336..4086c6cfb81 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -430,7 +430,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, // Delete the J2_jump if it's equivalent to a fall-through. if (AllowModify && JumpToBlock && MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { - DEBUG(dbgs() << "\nErasing the jump to successor block\n";); + LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";); I->eraseFromParent(); I = MBB.instr_end(); if (I == MBB.instr_begin()) @@ -499,8 +499,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, Cond.push_back(LastInst->getOperand(1)); return false; } - DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) - << " with one jump\n";); + LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) + << " with one jump\n";); // Otherwise, don't know what this is. return true; } @@ -547,8 +547,8 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, FBB = LastInst->getOperand(0).getMBB(); return false; } - DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) - << " with two jumps";); + LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) + << " with two jumps";); // Otherwise, can't handle this. return true; } @@ -557,7 +557,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); - DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB)); + LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB)); MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { @@ -629,7 +629,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset) // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset) unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); - DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB);); + LLVM_DEBUG(dbgs() << "\nInserting NVJump for " + << printMBBReference(MBB);); if (Cond[2].isReg()) { unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). @@ -1501,7 +1502,7 @@ bool HexagonInstrInfo::PredicateInstruction( MachineInstr &MI, ArrayRef<MachineOperand> Cond) const { if (Cond.empty() || isNewValueJump(Cond[0].getImm()) || isEndLoopN(Cond[0].getImm())) { - DEBUG(dbgs() << "\nCannot predicate:"; MI.dump();); + LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump();); return false; } int Opc = MI.getOpcode(); @@ -2251,13 +2252,13 @@ bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, bool isLate = isLateResultInstr(LRMI); bool isEarly = isEarlySourceInstr(ESMI); - DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- ")); - DEBUG(LRMI.dump()); - DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- ")); - DEBUG(ESMI.dump()); + LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- ")); + LLVM_DEBUG(LRMI.dump()); + LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- ")); + LLVM_DEBUG(ESMI.dump()); if (isLate && isEarly) { - DEBUG(dbgs() << "++Is Late Result feeding Early Source\n"); + LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n"); return true; } @@ -4174,7 +4175,7 @@ bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond, return false; assert(Cond.size() == 2); if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) { - DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); + LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop"); return false; } PredReg = Cond[1].getReg(); @@ -4276,9 +4277,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const { bool HexagonInstrInfo::invertAndChangeJumpTarget( MachineInstr &MI, MachineBasicBlock *NewTarget) const { - DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to " - << printMBBReference(*NewTarget); - MI.dump();); + LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to " + << printMBBReference(*NewTarget); + MI.dump();); assert(MI.isBranch()); unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); int TargetPos = MI.getNumOperands() - 1; @@ -4306,8 +4307,9 @@ void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const { for (unsigned insn = TargetOpcode::GENERIC_OP_END+1; insn < Hexagon::INSTRUCTION_LIST_END; ++insn) { NewMI = BuildMI(B, I, DL, get(insn)); - DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) << - " Class: " << NewMI->getDesc().getSchedClass()); + LLVM_DEBUG(dbgs() << "\n" + << getName(NewMI->getOpcode()) + << " Class: " << NewMI->getDesc().getSchedClass()); NewMI->eraseFromParent(); } /* --- The code above is used to generate complete set of Hexagon Insn --- */ @@ -4317,7 +4319,7 @@ void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const { // p -> NotP // NotP -> P bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const { - DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump()); + LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump()); MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode()))); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index d0bc2ed83a7..8b22d35cf9c 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -1758,15 +1758,15 @@ void PolynomialMultiplyRecognize::setupPostSimplifier(Simplifier &S) { } bool PolynomialMultiplyRecognize::recognize() { - DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n" - << *CurLoop << '\n'); + LLVM_DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n" + << *CurLoop << '\n'); // Restrictions: // - The loop must consist of a single block. // - The iteration count must be known at compile-time. // - The loop must have an induction variable starting from 0, and // incremented in each iteration of the loop. BasicBlock *LoopB = CurLoop->getHeader(); - DEBUG(dbgs() << "Loop header:\n" << *LoopB); + LLVM_DEBUG(dbgs() << "Loop header:\n" << *LoopB); if (LoopB != CurLoop->getLoopLatch()) return false; @@ -1788,7 +1788,8 @@ bool PolynomialMultiplyRecognize::recognize() { ParsedValues PV; Simplifier PreSimp; PV.IterCount = IterCount; - DEBUG(dbgs() << "Loop IV: " << *CIV << "\nIterCount: " << IterCount << '\n'); + LLVM_DEBUG(dbgs() << "Loop IV: " << *CIV << "\nIterCount: " << IterCount + << '\n'); setupPreSimplifier(PreSimp); @@ -1815,7 +1816,7 @@ bool PolynomialMultiplyRecognize::recognize() { Simplifier::Context C(SI); Value *T = PreSimp.simplify(C); SelectInst *SelI = (T && isa<SelectInst>(T)) ? cast<SelectInst>(T) : SI; - DEBUG(dbgs() << "scanSelect(pre-scan): " << PE(C, SelI) << '\n'); + LLVM_DEBUG(dbgs() << "scanSelect(pre-scan): " << PE(C, SelI) << '\n'); if (scanSelect(SelI, LoopB, EntryB, CIV, PV, true)) { FoundPreScan = true; if (SelI != SI) { @@ -1828,7 +1829,7 @@ bool PolynomialMultiplyRecognize::recognize() { } if (!FoundPreScan) { - DEBUG(dbgs() << "Have not found candidates for pmpy\n"); + LLVM_DEBUG(dbgs() << "Have not found candidates for pmpy\n"); return false; } @@ -1868,14 +1869,14 @@ bool PolynomialMultiplyRecognize::recognize() { SelectInst *SelI = dyn_cast<SelectInst>(&In); if (!SelI) continue; - DEBUG(dbgs() << "scanSelect: " << *SelI << '\n'); + LLVM_DEBUG(dbgs() << "scanSelect: " << *SelI << '\n'); FoundScan = scanSelect(SelI, LoopB, EntryB, CIV, PV, false); if (FoundScan) break; } assert(FoundScan); - DEBUG({ + LLVM_DEBUG({ StringRef PP = (PV.M ? "(P+M)" : "P"); if (!PV.Inv) dbgs() << "Found pmpy idiom: R = " << PP << ".Q\n"; @@ -2287,10 +2288,11 @@ CleanupAndExit: NewCall->setDebugLoc(DLoc); - DEBUG(dbgs() << " Formed " << (Overlap ? "memmove: " : "memcpy: ") - << *NewCall << "\n" - << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" - << " from store ptr=" << *StoreEv << " at: " << *SI << "\n"); + LLVM_DEBUG(dbgs() << " Formed " << (Overlap ? "memmove: " : "memcpy: ") + << *NewCall << "\n" + << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" + << " from store ptr=" << *StoreEv << " at: " << *SI + << "\n"); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 4376a30fdd9..74c550ce822 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -172,11 +172,11 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { Packet.push_back(SU); #ifndef NDEBUG - DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n"); + LLVM_DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n"); for (unsigned i = 0, e = Packet.size(); i != e; ++i) { - DEBUG(dbgs() << "\t[" << i << "] SU("); - DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); - DEBUG(Packet[i]->getInstr()->dump()); + LLVM_DEBUG(dbgs() << "\t[" << i << "] SU("); + LLVM_DEBUG(dbgs() << Packet[i]->NodeNum << ")\t"); + LLVM_DEBUG(Packet[i]->getInstr()->dump()); } #endif @@ -187,10 +187,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { /// after setting up the current scheduling region. [RegionBegin, RegionEnd) /// only includes instructions that have DAG nodes, not scheduling boundaries. void VLIWMachineScheduler::schedule() { - DEBUG(dbgs() << "********** MI Converging Scheduling VLIW " - << printMBBReference(*BB) << " " << BB->getName() << " in_func " - << BB->getParent()->getName() << " at loop depth " - << MLI->getLoopDepth(BB) << " \n"); + LLVM_DEBUG(dbgs() << "********** MI Converging Scheduling VLIW " + << printMBBReference(*BB) << " " << BB->getName() + << " in_func " << BB->getParent()->getName() + << " at loop depth " << MLI->getLoopDepth(BB) << " \n"); buildDAGWithRegPressure(); @@ -205,24 +205,25 @@ void VLIWMachineScheduler::schedule() { // Initialize the strategy before modifying the DAG. SchedImpl->initialize(this); - DEBUG(unsigned maxH = 0; - for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - if (SUnits[su].getHeight() > maxH) - maxH = SUnits[su].getHeight(); - dbgs() << "Max Height " << maxH << "\n";); - DEBUG(unsigned maxD = 0; - for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - if (SUnits[su].getDepth() > maxD) - maxD = SUnits[su].getDepth(); - dbgs() << "Max Depth " << maxD << "\n";); - DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(this)); + LLVM_DEBUG(unsigned maxH = 0; + for (unsigned su = 0, e = SUnits.size(); su != e; + ++su) if (SUnits[su].getHeight() > maxH) maxH = + SUnits[su].getHeight(); + dbgs() << "Max Height " << maxH << "\n";); + LLVM_DEBUG(unsigned maxD = 0; + for (unsigned su = 0, e = SUnits.size(); su != e; + ++su) if (SUnits[su].getDepth() > maxD) maxD = + SUnits[su].getDepth(); + dbgs() << "Max Depth " << maxD << "\n";); + LLVM_DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su] + .dumpAll(this)); initQueues(TopRoots, BotRoots); bool IsTopNode = false; while (true) { - DEBUG(dbgs() << "** VLIWMachineScheduler::schedule picking next node\n"); + LLVM_DEBUG( + dbgs() << "** VLIWMachineScheduler::schedule picking next node\n"); SUnit *SU = SchedImpl->pickNode(IsTopNode); if (!SU) break; @@ -240,7 +241,7 @@ void VLIWMachineScheduler::schedule() { placeDebugValues(); - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Final schedule for " << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); @@ -379,8 +380,8 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() { } CheckPending = true; - DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle " - << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle " + << CurrCycle << '\n'); } /// Move the boundary of scheduled code by one SUnit. @@ -404,12 +405,12 @@ void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) { // TODO: Check if this SU must end a dispatch group. IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); if (startNewCycle) { - DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n'); bumpCycle(); } else - DEBUG(dbgs() << "*** IssueCount " << IssueCount - << " at cycle " << CurrCycle << '\n'); + LLVM_DEBUG(dbgs() << "*** IssueCount " << IssueCount << " at cycle " + << CurrCycle << '\n'); } /// Release pending ready nodes in to the available queue. This makes them @@ -582,22 +583,23 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (!SU || SU->isScheduled) return ResCount; - DEBUG(if (verbose) dbgs() << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); + LLVM_DEBUG(if (verbose) dbgs() + << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); // Forced priority is high. if (SU->isScheduleHigh) { ResCount += PriorityOne; - DEBUG(dbgs() << "H|"); + LLVM_DEBUG(dbgs() << "H|"); } unsigned IsAvailableAmt = 0; // Critical path first. if (Q.getID() == TopQID) { if (Top.isLatencyBound(SU)) { - DEBUG(if (verbose) dbgs() << "LB|"); + LLVM_DEBUG(if (verbose) dbgs() << "LB|"); ResCount += (SU->getHeight() * ScaleTwo); } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "h" << std::setw(3) << SU->getHeight() << "|"; dbgs() << dbgstr.str(); @@ -608,16 +610,16 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Top.ResourceModel->isResourceAvailable(SU, true)) { IsAvailableAmt = (PriorityTwo + PriorityThree); ResCount += IsAvailableAmt; - DEBUG(if (verbose) dbgs() << "A|"); + LLVM_DEBUG(if (verbose) dbgs() << "A|"); } else - DEBUG(if (verbose) dbgs() << " |"); + LLVM_DEBUG(if (verbose) dbgs() << " |"); } else { if (Bot.isLatencyBound(SU)) { - DEBUG(if (verbose) dbgs() << "LB|"); + LLVM_DEBUG(if (verbose) dbgs() << "LB|"); ResCount += (SU->getDepth() * ScaleTwo); } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "d" << std::setw(3) << SU->getDepth() << "|"; dbgs() << dbgstr.str(); @@ -628,9 +630,9 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Bot.ResourceModel->isResourceAvailable(SU, false)) { IsAvailableAmt = (PriorityTwo + PriorityThree); ResCount += IsAvailableAmt; - DEBUG(if (verbose) dbgs() << "A|"); + LLVM_DEBUG(if (verbose) dbgs() << "A|"); } else - DEBUG(if (verbose) dbgs() << " |"); + LLVM_DEBUG(if (verbose) dbgs() << " |"); } unsigned NumNodesBlocking = 0; @@ -652,7 +654,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, } ResCount += (NumNodesBlocking * ScaleTwo); - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "blk " << std::setw(2) << NumNodesBlocking << ")|"; dbgs() << dbgstr.str(); @@ -674,10 +676,10 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, (Delta.Excess.getUnitInc() || Delta.CriticalMax.getUnitInc() || Delta.CurrentMax.getUnitInc())) ResCount -= IsAvailableAmt; - DEBUG(if (verbose) { - dbgs() << "RP " << Delta.Excess.getUnitInc() << "/" - << Delta.CriticalMax.getUnitInc() <<"/" - << Delta.CurrentMax.getUnitInc() << ")|"; + LLVM_DEBUG(if (verbose) { + dbgs() << "RP " << Delta.Excess.getUnitInc() << "/" + << Delta.CriticalMax.getUnitInc() << "/" + << Delta.CurrentMax.getUnitInc() << ")|"; }); } @@ -689,11 +691,11 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (Q.getID() == TopQID && Top.ResourceModel->isResourceAvailable(SU, true)) { ResCount += PriorityTwo; - DEBUG(if (verbose) dbgs() << "C|"); + LLVM_DEBUG(if (verbose) dbgs() << "C|"); } else if (Q.getID() == BotQID && Bot.ResourceModel->isResourceAvailable(SU, false)) { ResCount += PriorityTwo; - DEBUG(if (verbose) dbgs() << "C|"); + LLVM_DEBUG(if (verbose) dbgs() << "C|"); } } @@ -705,7 +707,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, PI.getLatency() == 0 && Top.ResourceModel->isInPacket(PI.getSUnit())) { ResCount += PriorityThree; - DEBUG(if (verbose) dbgs() << "Z|"); + LLVM_DEBUG(if (verbose) dbgs() << "Z|"); } } } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { @@ -714,7 +716,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, SI.getLatency() == 0 && Bot.ResourceModel->isInPacket(SI.getSUnit())) { ResCount += PriorityThree; - DEBUG(if (verbose) dbgs() << "Z|"); + LLVM_DEBUG(if (verbose) dbgs() << "Z|"); } } } @@ -730,7 +732,7 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (PI.getLatency() > 0 && Top.ResourceModel->isInPacket(PI.getSUnit())) { ResCount -= PriorityOne; - DEBUG(if (verbose) dbgs() << "D|"); + LLVM_DEBUG(if (verbose) dbgs() << "D|"); } } } else { @@ -738,13 +740,13 @@ int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, if (SI.getLatency() > 0 && Bot.ResourceModel->isInPacket(SI.getSUnit())) { ResCount -= PriorityOne; - DEBUG(if (verbose) dbgs() << "D|"); + LLVM_DEBUG(if (verbose) dbgs() << "D|"); } } } } - DEBUG(if (verbose) { + LLVM_DEBUG(if (verbose) { std::stringstream dbgstr; dbgstr << "Total " << std::setw(4) << ResCount << ")"; dbgs() << dbgstr.str(); @@ -762,9 +764,9 @@ ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler:: pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Candidate) { ReadyQueue &Q = Zone.Available; - DEBUG(if (SchedDebugVerboseLevel > 1) - readyQueueVerboseDump(RPTracker, Candidate, Q); - else Q.dump();); + LLVM_DEBUG(if (SchedDebugVerboseLevel > 1) + readyQueueVerboseDump(RPTracker, Candidate, Q); + else Q.dump();); // getMaxPressureDelta temporarily modifies the tracker. RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker); @@ -781,7 +783,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, // Initialize the candidate if needed. if (!Candidate.SU) { - DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -794,7 +796,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, if (CurrentCost < 0 && Candidate.SCost < 0) { if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { - DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -805,7 +807,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, // Best cost. if (CurrentCost > Candidate.SCost) { - DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -818,7 +820,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, unsigned CandWeak = getWeakLeft(Candidate.SU, (Q.getID() == TopQID)); if (CurrWeak != CandWeak) { if (CurrWeak < CandWeak) { - DEBUG(traceCandidate("WCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("WCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -837,7 +839,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, CandSize = Candidate.SU->Preds.size(); } if (CurrSize > CandSize) { - DEBUG(traceCandidate("SPCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("SPCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -855,7 +857,7 @@ pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker, if (UseNewerCandidate && CurrentCost == Candidate.SCost) { if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) { - DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost)); + LLVM_DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost)); Candidate.SU = *I; Candidate.RPDelta = RPDelta; Candidate.SCost = CurrentCost; @@ -877,12 +879,12 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { // Schedule as far as possible in the direction of no choice. This is most // efficient, but also provides the best heuristics for CriticalPSets. if (SUnit *SU = Bot.pickOnlyChoice()) { - DEBUG(dbgs() << "Picked only Bottom\n"); + LLVM_DEBUG(dbgs() << "Picked only Bottom\n"); IsTopNode = false; return SU; } if (SUnit *SU = Top.pickOnlyChoice()) { - DEBUG(dbgs() << "Picked only Top\n"); + LLVM_DEBUG(dbgs() << "Picked only Top\n"); IsTopNode = true; return SU; } @@ -900,7 +902,7 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { // increase pressure for one of the excess PSets, then schedule in that // direction first to provide more freedom in the other direction. if (BotResult == SingleExcess || BotResult == SingleCritical) { - DEBUG(dbgs() << "Prefered Bottom Node\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom Node\n"); IsTopNode = false; return BotCand.SU; } @@ -911,29 +913,29 @@ SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) { assert(TopResult != NoCand && "failed to find the first candidate"); if (TopResult == SingleExcess || TopResult == SingleCritical) { - DEBUG(dbgs() << "Prefered Top Node\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node\n"); IsTopNode = true; return TopCand.SU; } // If either Q has a single candidate that minimizes pressure above the // original region's pressure pick it. if (BotResult == SingleMax) { - DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n"); IsTopNode = false; return BotCand.SU; } if (TopResult == SingleMax) { - DEBUG(dbgs() << "Prefered Top Node SingleMax\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node SingleMax\n"); IsTopNode = true; return TopCand.SU; } if (TopCand.SCost > BotCand.SCost) { - DEBUG(dbgs() << "Prefered Top Node Cost\n"); + LLVM_DEBUG(dbgs() << "Prefered Top Node Cost\n"); IsTopNode = true; return TopCand.SU; } // Otherwise prefer the bottom candidate in node order. - DEBUG(dbgs() << "Prefered Bottom in Node order\n"); + LLVM_DEBUG(dbgs() << "Prefered Bottom in Node order\n"); IsTopNode = false; return BotCand.SU; } @@ -976,11 +978,11 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) { if (SU->isBottomReady()) Bot.removeReady(SU); - DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom") - << " Scheduling instruction in cycle " - << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " (" << - reportPackets() << ")\n"; - SU->dump(DAG)); + LLVM_DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom") + << " Scheduling instruction in cycle " + << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " (" + << reportPackets() << ")\n"; + SU->dump(DAG)); return SU; } diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 3dace168284..9ba964a0aad 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -448,8 +448,8 @@ bool HexagonNewValueJump::isNewValueJumpCandidate( } bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { - DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" - << "********** Function: " << MF.getName() << "\n"); + LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" + << "********** Function: " << MF.getName() << "\n"); if (skipFunction(MF.getFunction())) return false; @@ -474,9 +474,10 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { MBBb != MBBe; ++MBBb) { MachineBasicBlock *MBB = &*MBBb; - DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); - DEBUG(MBB->dump()); - DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n"); + LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n"); + LLVM_DEBUG(MBB->dump()); + LLVM_DEBUG(dbgs() << "\n" + << "********** dumping instr bottom up **********\n"); bool foundJump = false; bool foundCompare = false; bool invertPredicate = false; @@ -501,7 +502,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated)) break; - DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n"); if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt || MI.getOpcode() == Hexagon::J2_jumptpt || diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 6d9c7820ac8..29c044b3b72 100644 --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -217,7 +217,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, NodeSet Visited, Defs; const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs); if (!P.second) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Unable to collect all reaching defs for use ***\n" << PrintNode<UseNode*>(UN, *DFG) << '\n' << "The program's complexity may exceed the limits.\n"; @@ -226,7 +226,7 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, } const auto &ReachingDefs = P.first; if (ReachingDefs.size() > 1) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "*** Multiple Reaching Defs found!!! ***\n"; for (auto DI : ReachingDefs) { NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI); @@ -244,15 +244,15 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeList &UNodeList) { for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { - DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[DefNode]: " + << Print<NodeAddr<DefNode *>>(DA, *DFG) << "\n"); RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG)); auto UseSet = LV->getAllReachedUses(DR, DA); for (auto UI : UseSet) { NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI); - DEBUG({ + LLVM_DEBUG({ NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG); dbgs() << "\t\t\t[Reached Use]: " << Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n"; @@ -262,8 +262,8 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG); NodeId id = PA.Id; const Liveness::RefMap &phiUse = LV->getRealUses(id); - DEBUG(dbgs() << "\t\t\t\tphi real Uses" - << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "\t\t\t\tphi real Uses" + << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); if (!phiUse.empty()) { for (auto I : phiUse) { if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) @@ -306,7 +306,8 @@ bool HexagonOptAddrMode::isSafeToExtLR(NodeAddr<StmtNode *> SN, NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(LRExtRR, IA); if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) || AA.Addr->getReachingDef() != LRExtRegRD) { - DEBUG(dbgs() << "isSafeToExtLR: Returning false; another reaching def\n"); + LLVM_DEBUG( + dbgs() << "isSafeToExtLR: Returning false; another reaching def\n"); return false; } @@ -396,8 +397,8 @@ bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN, NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber() - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber() + << ">]: " << *UseMI << "\n"); Changed |= updateAddUses(AddMI, UseMI); } @@ -451,7 +452,7 @@ bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR, } else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) { NodeList AddaslUseList; - DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); + LLVM_DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n"); getAllRealUses(SN, AddaslUseList); // Process phi nodes. if (allValidCandidates(SN, AddaslUseList) && @@ -515,8 +516,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, } else Changed = false; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -526,8 +527,8 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 4; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) @@ -568,8 +569,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, OpStart = 3; } Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) { short NewOpCode = HII->changeAddrMode_rr_io(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); @@ -578,8 +579,8 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, MIB.add(ImmOp); OpStart = 3; Changed = true; - DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); - DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); + LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); + LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); } if (Changed) for (unsigned i = OpStart; i < OpEnd; ++i) @@ -602,7 +603,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, unsigned ImmOpNum) { NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); + LLVM_DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n"); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -613,11 +614,11 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, "Can't transform this 'AddAsl' instruction!"); NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG); - DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) - << "\n"); + LLVM_DEBUG(dbgs() << "[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(UseIA, *DFG) << "\n"); MachineInstr *UseMI = UseIA.Addr->getCode(); - DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); const MCInstrDesc &UseMID = UseMI->getDesc(); assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset); @@ -695,9 +696,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { !MI->getOperand(2).isImm() || HII->isConstExtended(*MI))) continue; - DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: " - << *MI << "\n\t[InstrNode]: " - << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); + LLVM_DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) + << "]: " << *MI << "\n\t[InstrNode]: " + << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n'); NodeList UNodeList; getAllRealUses(SA, UNodeList); @@ -733,8 +734,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { bool KeepTfr = false; - DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() << "\n"); - DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); + LLVM_DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size() + << "\n"); + LLVM_DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n"); for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) { NodeAddr<UseNode *> UseN = *I; assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) && @@ -742,8 +744,8 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) { NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) - << ">]: " << *UseMI << "\n"); + LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) + << ">]: " << *UseMI << "\n"); int UseMOnum = -1; unsigned NumOperands = UseMI->getNumOperands(); @@ -793,8 +795,8 @@ bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) { Deleted.clear(); NodeAddr<FuncNode *> FA = DFG->getFunc(); - DEBUG(dbgs() << "==== [RefMap#]=====:\n " - << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); + LLVM_DEBUG(dbgs() << "==== [RefMap#]=====:\n " + << Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n"); for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG)) Changed |= processBlock(BA); diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 386e6cbad1f..e018785f24d 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -246,7 +246,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { if (FixedRegs[x]) continue; unsigned R = TargetRegisterInfo::index2VirtReg(x); - DEBUG(dbgs() << printReg(R, TRI) << " ~~"); + LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~"); USet &Asc = AssocMap[R]; for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end(); U != Z; ++U) { @@ -269,13 +269,13 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) { unsigned u = TargetRegisterInfo::virtReg2Index(T); if (FixedRegs[u]) continue; - DEBUG(dbgs() << ' ' << printReg(T, TRI)); + LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI)); Asc.insert(T); // Make it symmetric. AssocMap[T].insert(R); } } - DEBUG(dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); } UUMap R2P; @@ -468,7 +468,7 @@ bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM) if (FixedNum > 0 && LoopPhiNum > 0) TotalP -= 20*LoopPhiNum; - DEBUG(dbgs() << "Partition profit: " << TotalP << '\n'); + LLVM_DEBUG(dbgs() << "Partition profit: " << TotalP << '\n'); if (SplitAll) return true; return TotalP > 0; @@ -563,7 +563,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L, Rs.insert(CmpR1); Rs.insert(CmpR2); - DEBUG({ + LLVM_DEBUG({ dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: "; dump_partition(dbgs(), Rs, *TRI); dbgs() << '\n'; @@ -996,7 +996,7 @@ bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI, const UUPairMap &PairMap) { using namespace Hexagon; - DEBUG(dbgs() << "Splitting: " << *MI); + LLVM_DEBUG(dbgs() << "Splitting: " << *MI); bool Split = false; unsigned Opc = MI->getOpcode(); @@ -1130,8 +1130,8 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) { const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass; bool Changed = false; - DEBUG(dbgs() << "Splitting partition: "; dump_partition(dbgs(), Part, *TRI); - dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Splitting partition: "; + dump_partition(dbgs(), Part, *TRI); dbgs() << '\n'); UUPairMap PairMap; @@ -1148,8 +1148,9 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) { unsigned LoR = MRI->createVirtualRegister(IntRC); unsigned HiR = MRI->createVirtualRegister(IntRC); - DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " - << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n'); + LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> " + << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) + << '\n'); PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR))); } @@ -1189,8 +1190,8 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - DEBUG(dbgs() << "Splitting double registers in function: " - << MF.getName() << '\n'); + LLVM_DEBUG(dbgs() << "Splitting double registers in function: " + << MF.getName() << '\n'); auto &ST = MF.getSubtarget<HexagonSubtarget>(); TRI = ST.getRegisterInfo(); @@ -1204,7 +1205,7 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { collectIndRegs(IRM); partitionRegisters(P2Rs); - DEBUG({ + LLVM_DEBUG({ dbgs() << "Register partitioning: (partition #0 is fixed)\n"; for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) { dbgs() << '#' << I->first << " -> "; @@ -1222,7 +1223,8 @@ bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) { if (Limit >= 0 && Counter >= Limit) break; USet &Part = I->second; - DEBUG(dbgs() << "Calculating profit for partition #" << I->first << '\n'); + LLVM_DEBUG(dbgs() << "Calculating profit for partition #" << I->first + << '\n'); if (!isProfitable(Part, IRM)) continue; Counter++; diff --git a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp index 0f058106e32..991af047387 100644 --- a/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -474,7 +474,7 @@ bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG, // from OG was (in the order in which they appeared in the basic block). // (The ordering in OG does not have to match the order in the basic block.) bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) { - DEBUG({ + LLVM_DEBUG({ dbgs() << "Replacing:\n"; for (auto I : OG) dbgs() << " " << *I; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index ea86c9c42f4..e771f383dff 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -74,7 +74,7 @@ static cl::opt<bool> if (TraceGVPlacement) { \ TRACE_TO(errs(), X); \ } else { \ - DEBUG(TRACE_TO(dbgs(), X)); \ + LLVM_DEBUG(TRACE_TO(dbgs(), X)); \ } \ } while (false) #endif @@ -200,11 +200,11 @@ MCSection *HexagonTargetObjectFile::getExplicitSectionGlobal( bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { // Only global variables, not functions. - DEBUG(dbgs() << "Checking if value is in small-data, -G" - << SmallDataThreshold << ": \"" << GO->getName() << "\": "); + LLVM_DEBUG(dbgs() << "Checking if value is in small-data, -G" + << SmallDataThreshold << ": \"" << GO->getName() << "\": "); const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GO); if (!GVar) { - DEBUG(dbgs() << "no, not a global variable\n"); + LLVM_DEBUG(dbgs() << "no, not a global variable\n"); return false; } @@ -213,19 +213,19 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, // small data or not. This is how we can support mixing -G0/-G8 in LTO. if (GVar->hasSection()) { bool IsSmall = isSmallDataSection(GVar->getSection()); - DEBUG(dbgs() << (IsSmall ? "yes" : "no") << ", has section: " - << GVar->getSection() << '\n'); + LLVM_DEBUG(dbgs() << (IsSmall ? "yes" : "no") + << ", has section: " << GVar->getSection() << '\n'); return IsSmall; } if (GVar->isConstant()) { - DEBUG(dbgs() << "no, is a constant\n"); + LLVM_DEBUG(dbgs() << "no, is a constant\n"); return false; } bool IsLocal = GVar->hasLocalLinkage(); if (!StaticsInSData && IsLocal) { - DEBUG(dbgs() << "no, is static\n"); + LLVM_DEBUG(dbgs() << "no, is static\n"); return false; } @@ -234,7 +234,7 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, GType = PT->getElementType(); if (isa<ArrayType>(GType)) { - DEBUG(dbgs() << "no, is an array\n"); + LLVM_DEBUG(dbgs() << "no, is an array\n"); return false; } @@ -244,22 +244,22 @@ bool HexagonTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, // these objects end up in the sdata, the references will still be valid. if (StructType *ST = dyn_cast<StructType>(GType)) { if (ST->isOpaque()) { - DEBUG(dbgs() << "no, has opaque type\n"); + LLVM_DEBUG(dbgs() << "no, has opaque type\n"); return false; } } unsigned Size = GVar->getParent()->getDataLayout().getTypeAllocSize(GType); if (Size == 0) { - DEBUG(dbgs() << "no, has size 0\n"); + LLVM_DEBUG(dbgs() << "no, has size 0\n"); return false; } if (Size > SmallDataThreshold) { - DEBUG(dbgs() << "no, size exceeds sdata threshold: " << Size << '\n'); + LLVM_DEBUG(dbgs() << "no, size exceeds sdata threshold: " << Size << '\n'); return false; } - DEBUG(dbgs() << "yes\n"); + LLVM_DEBUG(dbgs() << "yes\n"); return true; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 2ae48e3d68f..e44c7237a7e 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -375,7 +375,7 @@ bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI, void HexagonPacketizerList::cleanUpDotCur() { MachineInstr *MI = nullptr; for (auto BI : CurrentPacketMIs) { - DEBUG(dbgs() << "Cleanup packet has "; BI->dump();); + LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump();); if (HII->isDotCurInst(*BI)) { MI = BI; continue; @@ -390,7 +390,7 @@ void HexagonPacketizerList::cleanUpDotCur() { return; // We did not find a use of the CUR, so de-cur it. MI->setDesc(HII->get(HII->getNonDotCurOp(*MI))); - DEBUG(dbgs() << "Demoted CUR "; MI->dump();); + LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump();); } // Check to see if an instruction can be dot cur. @@ -414,11 +414,10 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI, return false; // Make sure candidate instruction uses cur. - DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; - MI.dump(); - dbgs() << "in packet\n";); + LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump(); + dbgs() << "in packet\n";); MachineInstr &MJ = *MII; - DEBUG({ + LLVM_DEBUG({ dbgs() << "Checking CUR against "; MJ.dump(); }); @@ -433,12 +432,12 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI, // Check for existing uses of a vector register within the packet which // would be affected by converting a vector load into .cur formt. for (auto BI : CurrentPacketMIs) { - DEBUG(dbgs() << "packet has "; BI->dump();); + LLVM_DEBUG(dbgs() << "packet has "; BI->dump();); if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo())) return false; } - DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump();); + LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump();); // We can convert the opcode into a .cur. return true; } @@ -1762,7 +1761,7 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, bool memShufDisabled = getmemShufDisabled(); if (memShufDisabled && !foundLSInPacket()) { setmemShufDisabled(false); - DEBUG(dbgs() << " Not added to NoShufPacket\n"); + LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n"); } memShufDisabled = getmemShufDisabled(); @@ -1781,7 +1780,7 @@ void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, CurrentPacketMIs.clear(); ResourceTracker->clearResources(); - DEBUG(dbgs() << "End packet\n"); + LLVM_DEBUG(dbgs() << "End packet\n"); } bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) { diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp index e94c2483751..9d1073346c7 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -364,17 +364,18 @@ bool HexagonVectorLoopCarriedReuse::canReplace(Instruction *I) { if (II && (II->getIntrinsicID() == Intrinsic::hexagon_V6_hi || II->getIntrinsicID() == Intrinsic::hexagon_V6_lo)) { - DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n"); + LLVM_DEBUG(dbgs() << "Not considering for reuse: " << *II << "\n"); return false; } return true; } void HexagonVectorLoopCarriedReuse::findValueToReuse() { for (auto *D : Dependences) { - DEBUG(dbgs() << "Processing dependence " << *(D->front()) << "\n"); + LLVM_DEBUG(dbgs() << "Processing dependence " << *(D->front()) << "\n"); if (D->iterations() > HexagonVLCRIterationLim) { - DEBUG(dbgs() << - ".. Skipping because number of iterations > than the limit\n"); + LLVM_DEBUG( + dbgs() + << ".. Skipping because number of iterations > than the limit\n"); continue; } @@ -382,7 +383,8 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { Instruction *BEInst = D->back(); int Iters = D->iterations(); BasicBlock *BB = PN->getParent(); - DEBUG(dbgs() << "Checking if any uses of " << *PN << " can be reused\n"); + LLVM_DEBUG(dbgs() << "Checking if any uses of " << *PN + << " can be reused\n"); SmallVector<Instruction *, 4> PNUsers; for (auto UI = PN->use_begin(), E = PN->use_end(); UI != E; ++UI) { @@ -392,7 +394,8 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { if (User->getParent() != BB) continue; if (ReplacedInsts.count(User)) { - DEBUG(dbgs() << *User << " has already been replaced. Skipping...\n"); + LLVM_DEBUG(dbgs() << *User + << " has already been replaced. Skipping...\n"); continue; } if (isa<PHINode>(User)) @@ -404,7 +407,7 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { PNUsers.push_back(User); } - DEBUG(dbgs() << PNUsers.size() << " use(s) of the PHI in the block\n"); + LLVM_DEBUG(dbgs() << PNUsers.size() << " use(s) of the PHI in the block\n"); // For each interesting use I of PN, find an Instruction BEUser that // performs the same operation as I on BEInst and whose other operands, @@ -440,7 +443,7 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { } } if (BEUser) { - DEBUG(dbgs() << "Found Value for reuse.\n"); + LLVM_DEBUG(dbgs() << "Found Value for reuse.\n"); ReuseCandidate.Inst2Replace = I; ReuseCandidate.BackedgeInst = BEUser; return; @@ -461,7 +464,7 @@ Value *HexagonVectorLoopCarriedReuse::findValueInBlock(Value *Op, } void HexagonVectorLoopCarriedReuse::reuseValue() { - DEBUG(dbgs() << ReuseCandidate); + LLVM_DEBUG(dbgs() << ReuseCandidate); Instruction *Inst2Replace = ReuseCandidate.Inst2Replace; Instruction *BEInst = ReuseCandidate.BackedgeInst; int NumOperands = Inst2Replace->getNumOperands(); @@ -486,7 +489,7 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { } } - DEBUG(dbgs() << "reuseValue is making the following changes\n"); + LLVM_DEBUG(dbgs() << "reuseValue is making the following changes\n"); SmallVector<Instruction *, 4> InstsInPreheader; for (int i = 0; i < Iterations; ++i) { @@ -507,8 +510,8 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { InstsInPreheader.push_back(InstInPreheader); InstInPreheader->setName(Inst2Replace->getName() + ".hexagon.vlcr"); InstInPreheader->insertBefore(LoopPH->getTerminator()); - DEBUG(dbgs() << "Added " << *InstInPreheader << " to " << LoopPH->getName() - << "\n"); + LLVM_DEBUG(dbgs() << "Added " << *InstInPreheader << " to " + << LoopPH->getName() << "\n"); } BasicBlock *BB = BEInst->getParent(); IRBuilder<> IRB(BB); @@ -520,7 +523,8 @@ void HexagonVectorLoopCarriedReuse::reuseValue() { NewPhi = IRB.CreatePHI(InstInPreheader->getType(), 2); NewPhi->addIncoming(InstInPreheader, LoopPH); NewPhi->addIncoming(BEVal, BB); - DEBUG(dbgs() << "Adding " << *NewPhi << " to " << BB->getName() << "\n"); + LLVM_DEBUG(dbgs() << "Adding " << *NewPhi << " to " << BB->getName() + << "\n"); BEVal = NewPhi; } // We are in LCSSA form. So, a value defined inside the Loop is used only @@ -539,7 +543,7 @@ bool HexagonVectorLoopCarriedReuse::doVLCR() { bool Changed = false; bool Continue; - DEBUG(dbgs() << "Working on Loop: " << *CurLoop->getHeader() << "\n"); + LLVM_DEBUG(dbgs() << "Working on Loop: " << *CurLoop->getHeader() << "\n"); do { // Reset datastructures. Dependences.clear(); @@ -626,10 +630,9 @@ void HexagonVectorLoopCarriedReuse::findLoopCarriedDeps() { else delete D; } - DEBUG(dbgs() << "Found " << Dependences.size() << " dependences\n"); - DEBUG(for (size_t i = 0; i < Dependences.size(); ++i) { - dbgs() << *Dependences[i] << "\n"; - }); + LLVM_DEBUG(dbgs() << "Found " << Dependences.size() << " dependences\n"); + LLVM_DEBUG(for (size_t i = 0; i < Dependences.size(); + ++i) { dbgs() << *Dependences[i] << "\n"; }); } Pass *llvm::createHexagonVectorLoopCarriedReusePass() { diff --git a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp index ddd668b2cb1..18d2f2f4acd 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -144,14 +144,15 @@ bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) { unsigned Reg = 0; if (getInstrVecReg(*MII, Reg)) { VecPrintList.push_back((&*MII)); - DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump()); + LLVM_DEBUG(dbgs() << "Found vector reg inside bundle \n"; + MII->dump()); } } } else { unsigned Reg = 0; if (getInstrVecReg(MI, Reg)) { VecPrintList.push_back(&MI); - DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); + LLVM_DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); } } } @@ -163,33 +164,33 @@ bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) { for (auto *I : VecPrintList) { DebugLoc DL = I->getDebugLoc(); MachineBasicBlock *MBB = I->getParent(); - DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); + LLVM_DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); unsigned Reg = 0; if (!getInstrVecReg(*I, Reg)) llvm_unreachable("Need a vector reg"); MachineBasicBlock::instr_iterator MII = I->getIterator(); if (I->isInsideBundle()) { - DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); + LLVM_DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); while (MBB->instr_end() != MII && MII->isInsideBundle()) MII++; } else { - DEBUG(dbgs() << "add after instruction\n"; I->dump()); + LLVM_DEBUG(dbgs() << "add after instruction\n"; I->dump()); MII++; } if (MBB->instr_end() == MII) continue; if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { - DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); addAsmInstr(MBB, Reg, MII, DL, QII, Fn); } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { - DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, MII, DL, QII, Fn); addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, MII, DL, QII, Fn); } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { - DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n'); + LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); addAsmInstr(MBB, Reg, MII, DL, QII, Fn); } else llvm_unreachable("Bad Vector reg"); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index fe54c19370b..584f35e0051 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -510,17 +510,15 @@ public: break; } - DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" << - (unsigned)Kind << ")\n"); - DEBUG(uint32_t OldData = 0; - for (unsigned i = 0; i < NumBytes; i++) - OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << - ": AValue=0x"; dbgs().write_hex(FixupValue) << - ": Offset=" << Offset << - ": Size=" << Data.size() << - ": OInst=0x"; dbgs().write_hex(OldData) << - ": Reloc=0x"; dbgs().write_hex(Reloc);); + LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" + << (unsigned)Kind << ")\n"); + LLVM_DEBUG( + uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x"; + dbgs().write_hex(FixupValue) + << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x"; + dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc);); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. The Value has been "split up" into the @@ -530,10 +528,10 @@ public: InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc } - DEBUG(uint32_t NewData = 0; - for (unsigned i = 0; i < NumBytes; i++) - NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); + LLVM_DEBUG(uint32_t NewData = 0; + for (unsigned i = 0; i < NumBytes; i++) NewData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); } bool isInstRelaxable(MCInst const &HMI) const { @@ -689,8 +687,9 @@ public: ParseEnd = 0x0000c000; // End of packet parse-bits. while(Count % HEXAGON_INSTR_SIZE) { - DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << - Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); + LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" + << Count % HEXAGON_INSTR_SIZE << "/" + << HEXAGON_INSTR_SIZE << "\n"); --Count; OW->write8(0); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 91500d909a1..555386b8464 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -372,7 +372,7 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, MCInst &HMB = const_cast<MCInst &>(MI); assert(HexagonMCInstrInfo::isBundle(HMB)); - DEBUG(dbgs() << "Encoding bundle\n";); + LLVM_DEBUG(dbgs() << "Encoding bundle\n";); State.Addend = 0; State.Extended = false; State.Bundle = &MI; @@ -415,8 +415,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // in the first place! assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && "pseudo-instruction found"); - DEBUG(dbgs() << "Encoding insn `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Encoding insn `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); Binary = getBinaryCodeForInstr(MI, Fixups, STI); unsigned Opc = MI.getOpcode(); @@ -424,8 +424,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // Check for unimplemented instructions. Immediate extenders // are encoded as zero, so they need to be accounted for. if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) { - DEBUG(dbgs() << "Unimplemented inst `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Unimplemented inst `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; @@ -630,13 +630,12 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, unsigned Opc = MCID.getOpcode(); unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); - DEBUG(dbgs() << "----------------------------------------\n" - << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) - << "\nOpcode: " << Opc - << "\nRelocation bits: " << FixupWidth - << "\nAddend: " << State.Addend - << "\nVariant: " << unsigned(VarKind) - << "\n----------------------------------------\n"); + LLVM_DEBUG(dbgs() << "----------------------------------------\n" + << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) + << "\nOpcode: " << Opc << "\nRelocation bits: " + << FixupWidth << "\nAddend: " << State.Addend + << "\nVariant: " << unsigned(VarKind) + << "\n----------------------------------------\n"); // Pick the applicable fixup kind for the symbol. // Handle special cases first, the rest will be looked up in the tables. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp index 127c97e342d..3eaef9ac741 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp @@ -205,7 +205,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, switch (L.getOpcode()) { default: - DEBUG(dbgs() << "Possible compound ignored\n"); + LLVM_DEBUG(dbgs() << "Possible compound ignored\n"); return CompoundInsn; case Hexagon::A2_tfrsi: @@ -233,7 +233,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeq: - DEBUG(dbgs() << "CX: C2_cmpeq\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeq\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -246,7 +246,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgt: - DEBUG(dbgs() << "CX: C2_cmpgt\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgt\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -259,7 +259,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtu: - DEBUG(dbgs() << "CX: C2_cmpgtu\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtu\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -272,7 +272,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeqi: - DEBUG(dbgs() << "CX: C2_cmpeqi\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeqi\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -290,7 +290,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgti: - DEBUG(dbgs() << "CX: C2_cmpgti\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgti\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -308,7 +308,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtui: - DEBUG(dbgs() << "CX: C2_cmpgtui\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtui\n"); Rs = L.getOperand(1); compoundOpcode = cmpgtuiBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -319,7 +319,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::S2_tstbit_i: - DEBUG(dbgs() << "CX: S2_tstbit_i\n"); + LLVM_DEBUG(dbgs() << "CX: S2_tstbit_i\n"); Rs = L.getOperand(1); compoundOpcode = tstBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -372,14 +372,14 @@ static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, BExtended = true; continue; } - DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," - << Inst->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," + << Inst->getOpcode() << "\n"); if (isOrderedCompoundPair(*Inst, BExtended, *JumpInst, JExtended)) { MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst); if (CompoundInsn) { - DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," - << JumpInst->getOpcode() << " Compounds to " - << CompoundInsn->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," + << JumpInst->getOpcode() << " Compounds to " + << CompoundInsn->getOpcode() << "\n"); J->setInst(CompoundInsn); MCI.erase(B); return true; @@ -422,7 +422,7 @@ void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo co if (StartedValid && !llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) { - DEBUG(dbgs() << "Found ERROR\n"); + LLVM_DEBUG(dbgs() << "Found ERROR\n"); MCI = OriginalBundle; } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index fd064416fd9..b208a366812 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -1045,8 +1045,8 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, bool bisReversable = true; if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) && isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) { - DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j - << "\n"); + LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j + << "\n"); bisReversable = false; } if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf @@ -1066,14 +1066,14 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(j, k, iClass)); - DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); continue; } else { - DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } // Try reverse. @@ -1091,13 +1091,15 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(k, j, iClass)); - DEBUG(dbgs() << "adding pair:" << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "adding pair:" << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } else { - DEBUG(dbgs() << "skipping pair: " << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "skipping pair: " << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 7bd54fdfa3d..4281144acae 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -38,7 +38,8 @@ void HexagonMCShuffler::init(MCInst &MCB) { // Copy the bundle for the shuffling. for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst &MI = *const_cast<MCInst *>(I.getInst()); - DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n'); + LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) + << '\n'); assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); if (!HexagonMCInstrInfo::isImmext(MI)) { @@ -98,7 +99,7 @@ bool HexagonMCShuffler::reshuffleTo(MCInst &MCB) { copyTo(MCB); return true; } - DEBUG(MCB.dump()); + LLVM_DEBUG(MCB.dump()); return false; } @@ -119,10 +120,10 @@ bool llvm::HexagonMCShuffle(MCContext &Context, bool Fatal, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } @@ -144,10 +145,10 @@ llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 7709a0f6162..59f3caa6af9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -641,14 +641,14 @@ bool HexagonShuffler::shuffle() { } for (iterator ISJ = begin(); ISJ != end(); ++ISJ) - DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { + LLVM_DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { dbgs() << '/'; dbgs().write_hex(ISJ->CVI.getUnits()) << '|'; dbgs() << ISJ->CVI.getLanes(); } dbgs() << ':' << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode(); - dbgs() << '\n'); - DEBUG(dbgs() << '\n'); + dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); return Ok; } |
