diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td | 24 |
2 files changed, 19 insertions, 16 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index aae07119e95..785084c7090 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1957,7 +1957,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, // Misc: - ISD::SELECT, ISD::ConstantPool, + ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool, // Vector: ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, @@ -1979,12 +1979,15 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setTruncStoreAction(VT, TargetVT, Expand); } + // Normalize all inputs to SELECT to be vectors of i32. + if (VT.getVectorElementType() != MVT::i32) { + MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32); + setOperationAction(ISD::SELECT, VT, Promote); + AddPromotedToType(ISD::SELECT, VT, VT32); + } setOperationAction(ISD::SRA, VT, Custom); setOperationAction(ISD::SHL, VT, Custom); setOperationAction(ISD::SRL, VT, Custom); - - setOperationAction(ISD::BR_CC, VT, Expand); - setOperationAction(ISD::SELECT_CC, VT, Expand); } // Types natively supported: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td index eb14fe47786..9fbf94401da 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td @@ -977,18 +977,18 @@ let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { "", []>, Requires<[HasV60T,UseHVXDbl]>; } -class VSelPat<ValueType VT, RegisterClass RC, InstHexagon MI> - : Pat<(selectcc I32:$lhs, I32:$rhs, (VT RC:$tval), (VT RC:$fval), SETEQ), - (MI (C2_cmpeq I32:$lhs, I32:$rhs), RC:$tval, RC:$fval)>; - -def: VSelPat<v16i32, VectorRegs, PS_vselect>, - Requires<[HasV60T,UseHVXSgl]>; -def: VSelPat<v32i32, VecDblRegs, PS_wselect>, - Requires<[HasV60T,UseHVXSgl]>; -def: VSelPat<v32i32, VectorRegs128B, PS_vselect_128B>, - Requires<[HasV60T,UseHVXDbl]>; -def: VSelPat<v64i32, VecDblRegs128B, PS_wselect_128B>, - Requires<[HasV60T,UseHVXDbl]>; +let Predicates = [HasV60T,UseHVXSgl] in { + def: Pat<(select I1:$Pu, (v16i32 VectorRegs:$Vs), VectorRegs:$Vt), + (PS_vselect I1:$Pu, VectorRegs:$Vs, VectorRegs:$Vt)>; + def: Pat<(select I1:$Pu, (v32i32 VecDblRegs:$Vs), VecDblRegs:$Vt), + (PS_wselect I1:$Pu, VecDblRegs:$Vs, VecDblRegs:$Vt)>; +} +let Predicates = [HasV60T,UseHVXDbl] in { + def: Pat<(select I1:$Pu, (v32i32 VectorRegs128B:$Vs), VectorRegs128B:$Vt), + (PS_vselect_128B I1:$Pu, VectorRegs128B:$Vs, VectorRegs128B:$Vt)>; + def: Pat<(select I1:$Pu, (v64i32 VecDblRegs128B:$Vs), VecDblRegs128B:$Vt), + (PS_wselect_128B I1:$Pu, VecDblRegs128B:$Vs, VecDblRegs128B:$Vt)>; +} let hasNewValue = 1 in |
