diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/MCTargetDesc')
6 files changed, 67 insertions, 66 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index fe54c19370b..584f35e0051 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -510,17 +510,15 @@ public: break; } - DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" << - (unsigned)Kind << ")\n"); - DEBUG(uint32_t OldData = 0; - for (unsigned i = 0; i < NumBytes; i++) - OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << - ": AValue=0x"; dbgs().write_hex(FixupValue) << - ": Offset=" << Offset << - ": Size=" << Data.size() << - ": OInst=0x"; dbgs().write_hex(OldData) << - ": Reloc=0x"; dbgs().write_hex(Reloc);); + LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" + << (unsigned)Kind << ")\n"); + LLVM_DEBUG( + uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x"; + dbgs().write_hex(FixupValue) + << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x"; + dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc);); // For each byte of the fragment that the fixup touches, mask in the // bits from the fixup value. The Value has been "split up" into the @@ -530,10 +528,10 @@ public: InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc } - DEBUG(uint32_t NewData = 0; - for (unsigned i = 0; i < NumBytes; i++) - NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); - dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); + LLVM_DEBUG(uint32_t NewData = 0; + for (unsigned i = 0; i < NumBytes; i++) NewData |= + (InstAddr[i] << (i * 8)) & (0xff << (i * 8)); + dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";); } bool isInstRelaxable(MCInst const &HMI) const { @@ -689,8 +687,9 @@ public: ParseEnd = 0x0000c000; // End of packet parse-bits. while(Count % HEXAGON_INSTR_SIZE) { - DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" << - Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n"); + LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" + << Count % HEXAGON_INSTR_SIZE << "/" + << HEXAGON_INSTR_SIZE << "\n"); --Count; OW->write8(0); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 91500d909a1..555386b8464 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -372,7 +372,7 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, MCInst &HMB = const_cast<MCInst &>(MI); assert(HexagonMCInstrInfo::isBundle(HMB)); - DEBUG(dbgs() << "Encoding bundle\n";); + LLVM_DEBUG(dbgs() << "Encoding bundle\n";); State.Addend = 0; State.Extended = false; State.Bundle = &MI; @@ -415,8 +415,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // in the first place! assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && "pseudo-instruction found"); - DEBUG(dbgs() << "Encoding insn `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Encoding insn `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); Binary = getBinaryCodeForInstr(MI, Fixups, STI); unsigned Opc = MI.getOpcode(); @@ -424,8 +424,8 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, // Check for unimplemented instructions. Immediate extenders // are encoded as zero, so they need to be accounted for. if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) { - DEBUG(dbgs() << "Unimplemented inst `" - << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); + LLVM_DEBUG(dbgs() << "Unimplemented inst `" + << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; @@ -630,13 +630,12 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, unsigned Opc = MCID.getOpcode(); unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); - DEBUG(dbgs() << "----------------------------------------\n" - << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) - << "\nOpcode: " << Opc - << "\nRelocation bits: " << FixupWidth - << "\nAddend: " << State.Addend - << "\nVariant: " << unsigned(VarKind) - << "\n----------------------------------------\n"); + LLVM_DEBUG(dbgs() << "----------------------------------------\n" + << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) + << "\nOpcode: " << Opc << "\nRelocation bits: " + << FixupWidth << "\nAddend: " << State.Addend + << "\nVariant: " << unsigned(VarKind) + << "\n----------------------------------------\n"); // Pick the applicable fixup kind for the symbol. // Handle special cases first, the rest will be looked up in the tables. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp index 127c97e342d..3eaef9ac741 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp @@ -205,7 +205,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, switch (L.getOpcode()) { default: - DEBUG(dbgs() << "Possible compound ignored\n"); + LLVM_DEBUG(dbgs() << "Possible compound ignored\n"); return CompoundInsn; case Hexagon::A2_tfrsi: @@ -233,7 +233,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeq: - DEBUG(dbgs() << "CX: C2_cmpeq\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeq\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -246,7 +246,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgt: - DEBUG(dbgs() << "CX: C2_cmpgt\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgt\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -259,7 +259,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtu: - DEBUG(dbgs() << "CX: C2_cmpgtu\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtu\n"); Rs = L.getOperand(1); Rt = L.getOperand(2); @@ -272,7 +272,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpeqi: - DEBUG(dbgs() << "CX: C2_cmpeqi\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpeqi\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -290,7 +290,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgti: - DEBUG(dbgs() << "CX: C2_cmpgti\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgti\n"); Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(Value); (void)Success; assert(Success); @@ -308,7 +308,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::C2_cmpgtui: - DEBUG(dbgs() << "CX: C2_cmpgtui\n"); + LLVM_DEBUG(dbgs() << "CX: C2_cmpgtui\n"); Rs = L.getOperand(1); compoundOpcode = cmpgtuiBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -319,7 +319,7 @@ static MCInst *getCompoundInsn(MCContext &Context, MCInst const &L, break; case Hexagon::S2_tstbit_i: - DEBUG(dbgs() << "CX: S2_tstbit_i\n"); + LLVM_DEBUG(dbgs() << "CX: S2_tstbit_i\n"); Rs = L.getOperand(1); compoundOpcode = tstBitOpcode[getCompoundOp(R)]; CompoundInsn = new (Context) MCInst; @@ -372,14 +372,14 @@ static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, BExtended = true; continue; } - DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," - << Inst->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << "," + << Inst->getOpcode() << "\n"); if (isOrderedCompoundPair(*Inst, BExtended, *JumpInst, JExtended)) { MCInst *CompoundInsn = getCompoundInsn(Context, *Inst, *JumpInst); if (CompoundInsn) { - DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," - << JumpInst->getOpcode() << " Compounds to " - << CompoundInsn->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << "," + << JumpInst->getOpcode() << " Compounds to " + << CompoundInsn->getOpcode() << "\n"); J->setInst(CompoundInsn); MCI.erase(B); return true; @@ -422,7 +422,7 @@ void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo co if (StartedValid && !llvm::HexagonMCShuffle(Context, false, MCII, STI, MCI)) { - DEBUG(dbgs() << "Found ERROR\n"); + LLVM_DEBUG(dbgs() << "Found ERROR\n"); MCI = OriginalBundle; } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index fd064416fd9..b208a366812 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -1045,8 +1045,8 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, bool bisReversable = true; if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) && isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) { - DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j - << "\n"); + LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j + << "\n"); bisReversable = false; } if (HexagonMCInstrInfo::isMemReorderDisabled(MCB)) // }:mem_noshuf @@ -1066,14 +1066,14 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(j, k, iClass)); - DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); continue; } else { - DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } // Try reverse. @@ -1091,13 +1091,15 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, // Save off pairs for duplex checking. duplexToTry.push_back(DuplexCandidate(k, j, iClass)); - DEBUG(dbgs() << "adding pair:" << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "adding pair:" << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } else { - DEBUG(dbgs() << "skipping pair: " << k << "," << j << ":" - << MCB.getOperand(j).getInst()->getOpcode() << "," - << MCB.getOperand(k).getInst()->getOpcode() << "\n"); + LLVM_DEBUG(dbgs() + << "skipping pair: " << k << "," << j << ":" + << MCB.getOperand(j).getInst()->getOpcode() << "," + << MCB.getOperand(k).getInst()->getOpcode() << "\n"); } } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 7bd54fdfa3d..4281144acae 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -38,7 +38,8 @@ void HexagonMCShuffler::init(MCInst &MCB) { // Copy the bundle for the shuffling. for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst &MI = *const_cast<MCInst *>(I.getInst()); - DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n'); + LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) + << '\n'); assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); if (!HexagonMCInstrInfo::isImmext(MI)) { @@ -98,7 +99,7 @@ bool HexagonMCShuffler::reshuffleTo(MCInst &MCB) { copyTo(MCB); return true; } - DEBUG(MCB.dump()); + LLVM_DEBUG(MCB.dump()); return false; } @@ -119,10 +120,10 @@ bool llvm::HexagonMCShuffle(MCContext &Context, bool Fatal, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } @@ -144,10 +145,10 @@ llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, // * %d7 = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. - DEBUG(dbgs() << "Skipping empty bundle"); + LLVM_DEBUG(dbgs() << "Skipping empty bundle"); return false; } else if (!HexagonMCInstrInfo::isBundle(MCB)) { - DEBUG(dbgs() << "Skipping stand-alone insn"); + LLVM_DEBUG(dbgs() << "Skipping stand-alone insn"); return false; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 7709a0f6162..59f3caa6af9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -641,14 +641,14 @@ bool HexagonShuffler::shuffle() { } for (iterator ISJ = begin(); ISJ != end(); ++ISJ) - DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { + LLVM_DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { dbgs() << '/'; dbgs().write_hex(ISJ->CVI.getUnits()) << '|'; dbgs() << ISJ->CVI.getLanes(); } dbgs() << ':' << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode(); - dbgs() << '\n'); - DEBUG(dbgs() << '\n'); + dbgs() << '\n'); + LLVM_DEBUG(dbgs() << '\n'); return Ok; } |
