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Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp40
1 files changed, 20 insertions, 20 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index ec9d0b03275..55f31c62885 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -210,7 +210,7 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
for (auto &Op : MI->operands()) {
if (!Op.isReg())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
if (!Register::isVirtualRegister(R))
return true;
}
@@ -258,7 +258,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
// Skip non-registers or registers with subregisters.
if (&MO == &Op || !MO.isReg() || MO.getSubReg())
continue;
- unsigned T = MO.getReg();
+ Register T = MO.getReg();
if (!Register::isVirtualRegister(T)) {
FixedRegs.set(x);
continue;
@@ -372,8 +372,8 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
case Hexagon::A2_andp:
case Hexagon::A2_orp:
case Hexagon::A2_xorp: {
- unsigned Rs = MI->getOperand(1).getReg();
- unsigned Rt = MI->getOperand(2).getReg();
+ Register Rs = MI->getOperand(1).getReg();
+ Register Rt = MI->getOperand(2).getReg();
return profit(Rs) + profit(Rt);
}
@@ -499,7 +499,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
return;
assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");
// Expect a predicate register.
- unsigned PR = Cond[1].getReg();
+ Register PR = Cond[1].getReg();
assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
// Get the registers on which the loop controlling compare instruction
@@ -535,7 +535,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
if (!MI.isPHI())
break;
const MachineOperand &MD = MI.getOperand(0);
- unsigned R = MD.getReg();
+ Register R = MD.getReg();
if (MRI->getRegClass(R) == DoubleRC)
DP.push_back(R);
}
@@ -551,7 +551,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
// Get the output from the add. If it is one of the inputs to the
// loop-controlling compare instruction, then R is likely an induc-
// tion register.
- unsigned T = UseI->getOperand(0).getReg();
+ Register T = UseI->getOperand(0).getReg();
if (T == CmpR1 || T == CmpR2)
return false;
}
@@ -603,7 +603,7 @@ void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
continue;
}
// For register operands, set the subregister.
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
unsigned SR = Op.getSubReg();
bool isVirtReg = Register::isVirtualRegister(R);
bool isKill = Op.isKill();
@@ -674,7 +674,7 @@ void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
: MI->getOperand(2).getImm();
MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
- unsigned NewR = MRI->createVirtualRegister(RC);
+ Register NewR = MRI->createVirtualRegister(RC);
assert(!UpdOp.getSubReg() && "Def operand with subreg");
BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
.addReg(AdrOp.getReg(), RSA)
@@ -789,8 +789,8 @@ void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
assert(F != PairMap.end());
const UUPair &P = F->second;
- unsigned LoR = P.first;
- unsigned HiR = P.second;
+ Register LoR = P.first;
+ Register HiR = P.second;
unsigned Opc = MI->getOpcode();
bool Right = (Opc == S2_lsr_i_p || Opc == S2_asr_i_p);
@@ -813,7 +813,7 @@ void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
.addReg(Op1.getReg(), RS, HiSR);
} else if (S < 32) {
const TargetRegisterClass *IntRC = &IntRegsRegClass;
- unsigned TmpR = MRI->createVirtualRegister(IntRC);
+ Register TmpR = MRI->createVirtualRegister(IntRC);
// Expansion:
// Shift left: DR = shl R, #s
// LoR = shl R.lo, #s
@@ -953,12 +953,12 @@ void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
.addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
.addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
.addImm(S);
- unsigned TmpR1 = MRI->createVirtualRegister(IntRC);
+ Register TmpR1 = MRI->createVirtualRegister(IntRC);
BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
.addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
.addImm(S)
.addImm(32-S);
- unsigned TmpR2 = MRI->createVirtualRegister(IntRC);
+ Register TmpR2 = MRI->createVirtualRegister(IntRC);
BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
.addReg(Op1.getReg(), RS1, HiSR)
.addReg(TmpR1);
@@ -1002,7 +1002,7 @@ bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
switch (Opc) {
case TargetOpcode::PHI:
case TargetOpcode::COPY: {
- unsigned DstR = MI->getOperand(0).getReg();
+ Register DstR = MI->getOperand(0).getReg();
if (MRI->getRegClass(DstR) == DoubleRC) {
createHalfInstr(Opc, MI, PairMap, isub_lo);
createHalfInstr(Opc, MI, PairMap, isub_hi);
@@ -1079,7 +1079,7 @@ void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
for (auto &Op : MI->operands()) {
if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
UUPairMap::const_iterator F = PairMap.find(R);
if (F == PairMap.end())
continue;
@@ -1104,7 +1104,7 @@ void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
for (auto &Op : MI->operands()) {
if (!Op.isReg() || !Op.isUse())
continue;
- unsigned R = Op.getReg();
+ Register R = Op.getReg();
if (!Register::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
@@ -1113,7 +1113,7 @@ void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
if (F == PairMap.end())
continue;
const UUPair &Pr = F->second;
- unsigned NewDR = MRI->createVirtualRegister(DoubleRC);
+ Register NewDR = MRI->createVirtualRegister(DoubleRC);
BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
.addReg(Pr.first)
.addImm(Hexagon::isub_lo)
@@ -1145,8 +1145,8 @@ bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
U != W; ++U)
SplitIns.insert(U->getParent());
- unsigned LoR = MRI->createVirtualRegister(IntRC);
- unsigned HiR = MRI->createVirtualRegister(IntRC);
+ Register LoR = MRI->createVirtualRegister(IntRC);
+ Register HiR = MRI->createVirtualRegister(IntRC);
LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
<< printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
<< '\n');
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