diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonPeephole.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPeephole.cpp | 94 |
1 files changed, 43 insertions, 51 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index 6ddd3318f42..b064decc5c7 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -132,15 +132,13 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { PeepholeDoubleRegsMap.clear(); // Traverse the basic block. - for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); - ++MII) { - MachineInstr *MI = MII; + for (MachineInstr &MI : *MBB) { // Look for sign extends: // %vreg170<def> = SXTW %vreg166 - if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) { - assert (MI->getNumOperands() == 2); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src = MI->getOperand(1); + if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) { + assert(MI.getNumOperands() == 2); + MachineOperand &Dst = MI.getOperand(0); + MachineOperand &Src = MI.getOperand(1); unsigned DstReg = Dst.getReg(); unsigned SrcReg = Src.getReg(); // Just handle virtual registers. @@ -155,12 +153,11 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169) // %vreg170:DoublRegs, %vreg169:IntRegs - if (!DisableOptExtTo64 && - MI->getOpcode () == Hexagon::A4_combineir) { - assert (MI->getNumOperands() == 3); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src1 = MI->getOperand(1); - MachineOperand &Src2 = MI->getOperand(2); + if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) { + assert(MI.getNumOperands() == 3); + MachineOperand &Dst = MI.getOperand(0); + MachineOperand &Src1 = MI.getOperand(1); + MachineOperand &Src2 = MI.getOperand(2); if (Src1.getImm() != 0) continue; unsigned DstReg = Dst.getReg(); @@ -173,11 +170,11 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg. // and convert into // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg. - if (MI->getOpcode() == Hexagon::S2_lsr_i_p) { - assert(MI->getNumOperands() == 3); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src1 = MI->getOperand(1); - MachineOperand &Src2 = MI->getOperand(2); + if (MI.getOpcode() == Hexagon::S2_lsr_i_p) { + assert(MI.getNumOperands() == 3); + MachineOperand &Dst = MI.getOperand(0); + MachineOperand &Src1 = MI.getOperand(1); + MachineOperand &Src2 = MI.getOperand(2); if (Src2.getImm() != 32) continue; unsigned DstReg = Dst.getReg(); @@ -187,11 +184,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { } // Look for P=NOT(P). - if (!DisablePNotP && - (MI->getOpcode() == Hexagon::C2_not)) { - assert (MI->getNumOperands() == 2); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src = MI->getOperand(1); + if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) { + assert(MI.getNumOperands() == 2); + MachineOperand &Dst = MI.getOperand(0); + MachineOperand &Src = MI.getOperand(1); unsigned DstReg = Dst.getReg(); unsigned SrcReg = Src.getReg(); // Just handle virtual registers. @@ -206,10 +202,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Look for copy: // %vreg176<def> = COPY %vreg170:subreg_loreg - if (!DisableOptSZExt && MI->isCopy()) { - assert (MI->getNumOperands() == 2); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src = MI->getOperand(1); + if (!DisableOptSZExt && MI.isCopy()) { + assert(MI.getNumOperands() == 2); + MachineOperand &Dst = MI.getOperand(0); + MachineOperand &Src = MI.getOperand(1); // Make sure we are copying the lower 32 bits. if (Src.getSubReg() != Hexagon::subreg_loreg) @@ -222,22 +218,18 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Try to find in the map. if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) { // Change the 1st operand. - MI->RemoveOperand(1); - MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); + MI.RemoveOperand(1); + MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); } else { DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI = PeepholeDoubleRegsMap.find(SrcReg); if (DI != PeepholeDoubleRegsMap.end()) { std::pair<unsigned,unsigned> PeepholeSrc = DI->second; - MI->RemoveOperand(1); - MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first, - false /*isDef*/, - false /*isImp*/, - false /*isKill*/, - false /*isDead*/, - false /*isUndef*/, - false /*isEarlyClobber*/, - PeepholeSrc.second)); + MI.RemoveOperand(1); + MI.addOperand(MachineOperand::CreateReg( + PeepholeSrc.first, false /*isDef*/, false /*isImp*/, + false /*isKill*/, false /*isDead*/, false /*isUndef*/, + false /*isEarlyClobber*/, PeepholeSrc.second)); } } } @@ -246,8 +238,8 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Look for Predicated instructions. if (!DisablePNotP) { bool Done = false; - if (QII->isPredicated(*MI)) { - MachineOperand &Op0 = MI->getOperand(0); + if (QII->isPredicated(MI)) { + MachineOperand &Op0 = MI.getOperand(0); unsigned Reg0 = Op0.getReg(); const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); if (RC0->getID() == Hexagon::PredRegsRegClassID) { @@ -257,9 +249,9 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Try to find in the map. if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { // Change the 1st operand and, flip the opcode. - MI->getOperand(0).setReg(PeepholeSrc); - int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode()); - MI->setDesc(QII->get(NewOp)); + MI.getOperand(0).setReg(PeepholeSrc); + int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode()); + MI.setDesc(QII->get(NewOp)); Done = true; } } @@ -268,7 +260,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { if (!Done) { // Handle special instructions. - unsigned Op = MI->getOpcode(); + unsigned Op = MI.getOpcode(); unsigned NewOp = 0; unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices. @@ -285,15 +277,15 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { break; } if (NewOp) { - unsigned PSrc = MI->getOperand(PR).getReg(); + unsigned PSrc = MI.getOperand(PR).getReg(); if (unsigned POrig = PeepholeMap.lookup(PSrc)) { - MI->getOperand(PR).setReg(POrig); - MI->setDesc(QII->get(NewOp)); + MI.getOperand(PR).setReg(POrig); + MI.setDesc(QII->get(NewOp)); // Swap operands S1 and S2. - MachineOperand Op1 = MI->getOperand(S1); - MachineOperand Op2 = MI->getOperand(S2); - ChangeOpInto(MI->getOperand(S1), Op2); - ChangeOpInto(MI->getOperand(S2), Op1); + MachineOperand Op1 = MI.getOperand(S1); + MachineOperand Op2 = MI.getOperand(S2); + ChangeOpInto(MI.getOperand(S1), Op2); + ChangeOpInto(MI.getOperand(S2), Op1); } } // if (NewOp) } // if (!Done) |
