diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td | 822 |
1 files changed, 810 insertions, 12 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td index 1b24be47715..9f98da3a1de 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -1,4 +1,4 @@ -//===--- HexagonDepInstrFormats.td ----------------------------------------===// +//===- HexagonDepInstrFormats.td ------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,6 +6,9 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + class Enc_890909 : OpcodeHexagon { bits <5> Rs32; @@ -15,6 +18,18 @@ class Enc_890909 : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } +class Enc_9be1de : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_527412 : OpcodeHexagon { bits <2> Ps4; let Inst{17-16} = Ps4{1-0}; @@ -46,14 +61,23 @@ class Enc_27b757 : OpcodeHexagon { bits <5> Vs32; let Inst{4-0} = Vs32{4-0}; } -class Enc_5de85f : OpcodeHexagon { +class Enc_8d04c3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_1de724 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; let Inst{7-1} = Ii{8-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; } class Enc_0e41fa : OpcodeHexagon { bits <5> Vuu32; @@ -63,12 +87,48 @@ class Enc_0e41fa : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_2a736a : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3d6d37 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_a641d0 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_802dc0 : OpcodeHexagon { bits <1> Ii; let Inst{8-8} = Ii{0-0}; bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; } +class Enc_6a4549 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_6b197f : OpcodeHexagon { bits <4> Ii; let Inst{8-5} = Ii{3-0}; @@ -77,6 +137,14 @@ class Enc_6b197f : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_1f3376 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} class Enc_1f5d8f : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; @@ -165,6 +233,14 @@ class Enc_7eee72 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_310ba1 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} class Enc_d7dc10 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; @@ -191,6 +267,14 @@ class Enc_8dec2e : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_28dcbb : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} class Enc_eaa9f8 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -207,6 +291,14 @@ class Enc_509701 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_c84567 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_830e5d : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; @@ -218,6 +310,12 @@ class Enc_830e5d : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_ae0040 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <6> Sd64; + let Inst{5-0} = Sd64{5-0}; +} class Enc_79b8c8 : OpcodeHexagon { bits <6> Ii; let Inst{6-3} = Ii{5-2}; @@ -238,6 +336,16 @@ class Enc_58a8bf : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_e8ddd5 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_041d7b : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -261,6 +369,14 @@ class Enc_f44229 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_fc563d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_aad80c : OpcodeHexagon { bits <5> Vuu32; let Inst{12-8} = Vuu32{4-0}; @@ -432,6 +548,13 @@ class Enc_6a5972 : OpcodeHexagon { bits <4> Rt16; let Inst{11-8} = Rt16{3-0}; } +class Enc_ff3442 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} class Enc_53dca9 : OpcodeHexagon { bits <6> Ii; let Inst{11-8} = Ii{5-2}; @@ -456,6 +579,12 @@ class Enc_93af4c : OpcodeHexagon { bits <4> Rx16; let Inst{3-0} = Rx16{3-0}; } +class Enc_621fba : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; +} class Enc_5bdd42 : OpcodeHexagon { bits <7> Ii; let Inst{8-5} = Ii{6-3}; @@ -464,6 +593,14 @@ class Enc_5bdd42 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_ad9bef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} class Enc_71f1b4 : OpcodeHexagon { bits <6> Ii; let Inst{8-5} = Ii{5-2}; @@ -483,6 +620,12 @@ class Enc_14640c : OpcodeHexagon { let Inst{24-22} = n1{3-1}; let Inst{13-13} = n1{0-0}; } +class Enc_2516bf : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_31db33 : OpcodeHexagon { bits <2> Qt4; let Inst{6-5} = Qt4{1-0}; @@ -513,6 +656,24 @@ class Enc_784502 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_9a9d62 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3a81ac : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6413b6 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -592,6 +753,16 @@ class Enc_e39bb2 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_7db2f8 : OpcodeHexagon { + bits <5> Vu32; + let Inst{13-9} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_1b64fb : OpcodeHexagon { bits <16> Ii; let Inst{26-25} = Ii{15-14}; @@ -670,6 +841,10 @@ class Enc_fcf7a7 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_2c3281 : OpcodeHexagon { + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_55355c : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; @@ -745,6 +920,10 @@ class Enc_fef969 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_b2ffce : OpcodeHexagon { + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_63eaeb : OpcodeHexagon { bits <2> Ii; let Inst{1-0} = Ii{1-0}; @@ -769,6 +948,12 @@ class Enc_372c9d : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_9e9047 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} class Enc_4dff07 : OpcodeHexagon { bits <2> Qv4; let Inst{12-11} = Qv4{1-0}; @@ -815,6 +1000,16 @@ class Enc_b388cf : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_880793 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_ad1c74 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -854,6 +1049,16 @@ class Enc_5e87ce : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_158beb : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} class Enc_f7ea77 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -897,6 +1102,14 @@ class Enc_226535 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } +class Enc_96f0fd : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qdd8; + let Inst{2-0} = Qdd8{2-0}; +} class Enc_31aa6a : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -907,6 +1120,12 @@ class Enc_31aa6a : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_932b58 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} class Enc_397f23 : OpcodeHexagon { bits <8> Ii; let Inst{13-13} = Ii{7-7}; @@ -973,6 +1192,14 @@ class Enc_01d3d0 : OpcodeHexagon { bits <5> Vdd32; let Inst{4-0} = Vdd32{4-0}; } +class Enc_3126d7 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_b0e9d8 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1049,6 +1276,12 @@ class Enc_88c16c : OpcodeHexagon { bits <5> Rxx32; let Inst{4-0} = Rxx32{4-0}; } +class Enc_e7408c : OpcodeHexagon { + bits <6> Sss64; + let Inst{21-16} = Sss64{5-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_770858 : OpcodeHexagon { bits <2> Ps4; let Inst{6-5} = Ps4{1-0}; @@ -1090,6 +1323,16 @@ class Enc_412ff0 : OpcodeHexagon { bits <5> Rxx32; let Inst{12-8} = Rxx32{4-0}; } +class Enc_8e9fbd : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} class Enc_c9a18e : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -1134,6 +1377,16 @@ class Enc_d6990d : OpcodeHexagon { bits <5> Vxx32; let Inst{4-0} = Vxx32{4-0}; } +class Enc_6c4697 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6c9440 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1278,6 +1531,12 @@ class Enc_a803e0 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } +class Enc_fde0e3 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_45364e : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -1298,6 +1557,12 @@ class Enc_b909d2 : OpcodeHexagon { let Inst{13-13} = n1{1-1}; let Inst{8-8} = n1{0-0}; } +class Enc_790d6e : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_e6c957 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1358,6 +1623,14 @@ class Enc_0ed752 : OpcodeHexagon { bits <5> Cdd32; let Inst{4-0} = Cdd32{4-0}; } +class Enc_908985 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_143445 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1385,6 +1658,16 @@ class Enc_3e3989 : OpcodeHexagon { let Inst{25-22} = n1{4-1}; let Inst{8-8} = n1{0-0}; } +class Enc_12dd8f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_152467 : OpcodeHexagon { bits <5> Ii; let Inst{8-5} = Ii{4-1}; @@ -1393,6 +1676,14 @@ class Enc_152467 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_6b1bc4 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_daea09 : OpcodeHexagon { bits <17> Ii; let Inst{23-22} = Ii{16-15}; @@ -1421,6 +1712,32 @@ class Enc_a198f6 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_a265b7 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_4e4a80 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_8d5d98 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} class Enc_3dac0b : OpcodeHexagon { bits <2> Qt4; let Inst{6-5} = Qt4{1-0}; @@ -1463,6 +1780,16 @@ class Enc_2df31d : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_b0e553 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_25bef0 : OpcodeHexagon { bits <16> Ii; let Inst{26-25} = Ii{15-14}; @@ -1482,6 +1809,12 @@ class Enc_f82302 : OpcodeHexagon { let Inst{26-25} = n1{2-1}; let Inst{23-23} = n1{0-0}; } +class Enc_44271f : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} class Enc_83ee64 : OpcodeHexagon { bits <5> Ii; let Inst{12-8} = Ii{4-0}; @@ -1524,6 +1857,14 @@ class Enc_4df4e9 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_263841 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} class Enc_91b9fe : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -1564,6 +1905,11 @@ class Enc_bd1cbc : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_d0fe02 : OpcodeHexagon { + bits <5> Rxx32; + let Inst{20-16} = Rxx32{4-0}; + bits <0> sgp10; +} class Enc_a30110 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -1583,6 +1929,16 @@ class Enc_f3f408 : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_ce4c54 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_690862 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1593,6 +1949,20 @@ class Enc_690862 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_e570b0 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3c46e8 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_2a3787 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1640,6 +2010,22 @@ class Enc_729ff7 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_5883d0 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_ff0e49 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <6> Sdd64; + let Inst{5-0} = Sdd64{5-0}; +} class Enc_217147 : OpcodeHexagon { bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; @@ -1674,6 +2060,14 @@ class Enc_541f26 : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } +class Enc_9aae4a : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qd8; + let Inst{2-0} = Qd8{2-0}; +} class Enc_724154 : OpcodeHexagon { bits <6> II; let Inst{5-0} = II{5-0}; @@ -1781,6 +2175,12 @@ class Enc_22c845 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_ed5027 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} class Enc_9b0bc1 : OpcodeHexagon { bits <2> Pu4; let Inst{6-5} = Pu4{1-0}; @@ -1828,6 +2228,12 @@ class Enc_96ce4f : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_2bbae6 : OpcodeHexagon { + bits <6> Ss64; + let Inst{21-16} = Ss64{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} class Enc_143a3c : OpcodeHexagon { bits <6> Ii; let Inst{13-8} = Ii{5-0}; @@ -1959,6 +2365,26 @@ class Enc_b43b67 : OpcodeHexagon { bits <2> Qx4; let Inst{6-5} = Qx4{1-0}; } +class Enc_1cd70f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3a527f : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_4aca3a : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -1977,6 +2403,12 @@ class Enc_b38ffc : OpcodeHexagon { bits <4> Rt16; let Inst{3-0} = Rt16{3-0}; } +class Enc_5c3a80 : OpcodeHexagon { + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} class Enc_cda00a : OpcodeHexagon { bits <12> Ii; let Inst{19-16} = Ii{11-8}; @@ -1994,6 +2426,24 @@ class Enc_2fbf3c : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_a4ae28 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_dd5f9f : OpcodeHexagon { + bits <3> Qtt8; + let Inst{2-0} = Qtt8{2-0}; + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_70b24b : OpcodeHexagon { bits <6> Ii; let Inst{8-5} = Ii{5-2}; @@ -2040,6 +2490,16 @@ class Enc_08d755 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_a7ca29 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_1178da : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; @@ -2058,6 +2518,14 @@ class Enc_8dbe85 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_17a474 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_5a18b3 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -2118,6 +2586,14 @@ class Enc_12b6e9 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_9a895f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6f70ca : OpcodeHexagon { bits <8> Ii; let Inst{8-4} = Ii{7-3}; @@ -2130,6 +2606,12 @@ class Enc_7222b7 : OpcodeHexagon { } class Enc_e3b0c4 : OpcodeHexagon { } +class Enc_d7e8ba : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_a255dc : OpcodeHexagon { bits <3> Ii; let Inst{10-8} = Ii{2-0}; @@ -2138,6 +2620,24 @@ class Enc_a255dc : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_cb785b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_5b76ab : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_cb4b4e : OpcodeHexagon { bits <2> Pu4; let Inst{6-5} = Pu4{1-0}; @@ -2148,6 +2648,24 @@ class Enc_cb4b4e : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_fbacc2 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_2ad23d : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_9cdba7 : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; @@ -2165,6 +2683,10 @@ class Enc_5cd7e9 : OpcodeHexagon { bits <5> Ryy32; let Inst{4-0} = Ryy32{4-0}; } +class Enc_e7c9de : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; +} class Enc_454a26 : OpcodeHexagon { bits <2> Pt4; let Inst{9-8} = Pt4{1-0}; @@ -2193,6 +2715,16 @@ class Enc_c175d0 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_16c48b : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_895bd9 : OpcodeHexagon { bits <2> Qu4; let Inst{9-8} = Qu4{1-0}; @@ -2254,6 +2786,14 @@ class Enc_d2c7f1 : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } +class Enc_dcfcbb : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_3680c2 : OpcodeHexagon { bits <7> Ii; let Inst{11-5} = Ii{6-0}; @@ -2282,6 +2822,32 @@ class Enc_e957fb : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } +class Enc_2146c1 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qss8; + let Inst{2-0} = Qss8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_a662ae : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_8f7cc3 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{10-8} = Qtt8{2-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} class Enc_c9e3bc : OpcodeHexagon { bits <4> Ii; let Inst{13-13} = Ii{3-3}; @@ -2314,6 +2880,40 @@ class Enc_0b2e5b : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_6f83e7 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_46f33d : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_c1652e : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_b5b643 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_85daf5 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_d483b9 : OpcodeHexagon { bits <1> Ii; let Inst{5-5} = Ii{0-0}; @@ -2346,6 +2946,26 @@ class Enc_70fb07 : OpcodeHexagon { bits <5> Rxx32; let Inst{4-0} = Rxx32{4-0}; } +class Enc_6c9ee0 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_72a92d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_44661f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_277737 : OpcodeHexagon { bits <8> Ii; let Inst{22-21} = Ii{7-6}; @@ -2496,6 +3116,14 @@ class Enc_8e583a : OpcodeHexagon { let Inst{25-23} = n1{3-1}; let Inst{13-13} = n1{0-0}; } +class Enc_334c2b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_b886fd : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -2549,12 +3177,36 @@ class Enc_8dbdfe : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_7dc746 : OpcodeHexagon { + bits <3> Quu8; + let Inst{10-8} = Quu8{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} class Enc_90cd8b : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_b8513b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_b3bac4 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_bd0b33 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -2564,6 +3216,24 @@ class Enc_bd0b33 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_843e80 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <3> Qxx8; + let Inst{2-0} = Qxx8{2-0}; +} +class Enc_8b8927 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} class Enc_c7cd90 : OpcodeHexagon { bits <4> Ii; let Inst{6-3} = Ii{3-0}; @@ -2711,15 +3381,24 @@ class Enc_1a9974 : OpcodeHexagon { bits <5> Rtt32; let Inst{4-0} = Rtt32{4-0}; } -class Enc_1de724 : OpcodeHexagon { +class Enc_9ce456 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5de85f : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-22} = n1{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; } class Enc_dd766a : OpcodeHexagon { bits <5> Vu32; @@ -2737,6 +3416,14 @@ class Enc_0b51ce : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_b5e54d : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_b4e6cf : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -2755,6 +3442,12 @@ class Enc_44215c : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_0aa344 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_a21d47 : OpcodeHexagon { bits <6> Ii; let Inst{10-5} = Ii{5-0}; @@ -2786,6 +3479,16 @@ class Enc_645d54 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_b5d5a7 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; +} class Enc_667b39 : OpcodeHexagon { bits <5> Css32; let Inst{20-16} = Css32{4-0}; @@ -2843,6 +3546,16 @@ class Enc_b8c967 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_f106e0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <5> Vt32; + let Inst{13-9} = Vt32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; +} class Enc_fb6577 : OpcodeHexagon { bits <2> Pu4; let Inst{9-8} = Pu4{1-0}; @@ -2851,6 +3564,20 @@ class Enc_fb6577 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_37c406 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <4> Vdd16; + let Inst{7-4} = Vdd16{3-0}; +} +class Enc_403871 : OpcodeHexagon { + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_2bae10 : OpcodeHexagon { bits <4> Ii; let Inst{10-8} = Ii{3-1}; @@ -2859,6 +3586,22 @@ class Enc_2bae10 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_f3adb6 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_aac08c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_c4dc92 : OpcodeHexagon { bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; @@ -3000,6 +3743,13 @@ class Enc_134437 : OpcodeHexagon { bits <2> Qd4; let Inst{1-0} = Qd4{1-0}; } +class Enc_33f8ba : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_97d666 : OpcodeHexagon { bits <4> Rs16; let Inst{7-4} = Rs16{3-0}; @@ -3016,6 +3766,16 @@ class Enc_f82eaf : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_57e245 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} class Enc_69d63b : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -3082,6 +3842,24 @@ class Enc_7eaeb6 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_274a4c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_aceeef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_f55a0c : OpcodeHexagon { bits <6> Ii; let Inst{11-8} = Ii{5-2}; @@ -3120,6 +3898,16 @@ class Enc_7b523d : OpcodeHexagon { bits <5> Vxx32; let Inst{4-0} = Vxx32{4-0}; } +class Enc_c39a8b : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; +} class Enc_47ef61 : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; @@ -3229,6 +4017,16 @@ class Enc_eca7c8 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } +class Enc_598f6c : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_41dcc3 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_4b39e4 : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; |
