diff options
Diffstat (limited to 'llvm/lib/Target/CellSPU')
| -rw-r--r-- | llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUTargetMachine.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUTargetMachine.h | 8 |
3 files changed, 12 insertions, 11 deletions
diff --git a/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp index d5af2a88aed..5ce14c99cd1 100644 --- a/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp +++ b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -62,11 +62,12 @@ static MCAsmInfo *createSPUMCAsmInfo(const Target &T, StringRef TT) { } static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, - CodeModel::Model CM) { + CodeModel::Model CM, + CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); // For the time being, use static relocations, since there's really no // support for PIC yet. - X->InitMCCodeGenInfo(Reloc::Static, CM); + X->InitMCCodeGenInfo(Reloc::Static, CM, OL); return X; } diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp index 93a7f6e3650..69403160ac0 100644 --- a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -34,8 +34,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM) - : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), @@ -49,8 +50,7 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool SPUTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { +bool SPUTargetMachine::addInstSelector(PassManagerBase &PM) { // Install an instruction selector. PM.add(createSPUISelDag(*this)); return false; @@ -58,7 +58,7 @@ bool SPUTargetMachine::addInstSelector(PassManagerBase &PM, // passes to run just before printing the assembly bool SPUTargetMachine:: -addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { +addPreEmitPass(PassManagerBase &PM) { // load the TCE instruction scheduler, if available via // loaded plugins typedef llvm::FunctionPass* (*BuilderFunc)(const char*); diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.h b/llvm/lib/Target/CellSPU/SPUTargetMachine.h index fffe77cabba..909f12e4ff7 100644 --- a/llvm/lib/Target/CellSPU/SPUTargetMachine.h +++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.h @@ -40,7 +40,8 @@ class SPUTargetMachine : public LLVMTargetMachine { public: SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { @@ -81,9 +82,8 @@ public: } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel); - virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level); + virtual bool addInstSelector(PassManagerBase &PM); + virtual bool addPreEmitPass(PassManagerBase &); }; } // end namespace llvm |
