diff options
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 365030f4fba..eaa899576b7 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2692,6 +2692,17 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) { case ARM::tSUBi3: case ARM::tSUBi8: case ARM::tMUL: + case ARM::tADC: + case ARM::tSBC: + case ARM::tRSB: + case ARM::tAND: + case ARM::tORR: + case ARM::tEOR: + case ARM::tBIC: + case ARM::tMVN: + case ARM::tASRri: + case ARM::tASRrr: + case ARM::tROR: IsThumb1 = true; LLVM_FALLTHROUGH; case ARM::RSBrr: @@ -2814,20 +2825,22 @@ bool ARMBaseInstrInfo::optimizeCompareInstr( // CMP. This peephole works on the vregs, so is still in SSA form. As a // consequence, the movs won't redefine/kill the MUL operands which would // make this reordering illegal. + const TargetRegisterInfo *TRI = &getRegisterInfo(); if (MI && IsThumb1) { --I; - bool CanReorder = true; - const bool HasStmts = I != E; - for (; I != E; --I) { - if (I->getOpcode() != ARM::tMOVi8) { - CanReorder = false; - break; + if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { + bool CanReorder = true; + for (; I != E; --I) { + if (I->getOpcode() != ARM::tMOVi8) { + CanReorder = false; + break; + } + } + if (CanReorder) { + MI = MI->removeFromParent(); + E = CmpInstr; + CmpInstr.getParent()->insert(E, MI); } - } - if (HasStmts && CanReorder) { - MI = MI->removeFromParent(); - E = CmpInstr; - CmpInstr.getParent()->insert(E, MI); } I = CmpInstr; E = MI; @@ -2835,7 +2848,6 @@ bool ARMBaseInstrInfo::optimizeCompareInstr( // Check that CPSR isn't set between the comparison instruction and the one we // want to change. At the same time, search for SubAdd. - const TargetRegisterInfo *TRI = &getRegisterInfo(); bool SubAddIsThumb1 = false; do { const MachineInstr &Instr = *--I; |

