diff options
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index 357e5a13784..6db3ca76187 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -148,7 +148,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_ICMP, 1, Ty}, Legal); if (!ST.useSoftFloat() && ST.hasVFP2()) { - for (unsigned BinOp : {G_FADD, G_FSUB}) + for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL}) for (auto Ty : {s32, s64}) setAction({BinOp, Ty}, Legal); @@ -159,7 +159,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_FCMP, 1, s32}, Legal); setAction({G_FCMP, 1, s64}, Legal); } else { - for (unsigned BinOp : {G_FADD, G_FSUB}) + for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL}) for (auto Ty : {s32, s64}) setAction({BinOp, Ty}, Libcall); diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 62bcc869d30..bcae1c93974 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -243,7 +243,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { break; } case G_FADD: - case G_FSUB: { + case G_FSUB: + case G_FMUL: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] |
