diff options
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index c5b2d2d5968..f837db56264 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5721,7 +5721,8 @@ void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, Mnemonic == "vudot" || Mnemonic == "vsdot" || Mnemonic == "vcmla" || Mnemonic == "vcadd" || Mnemonic == "vfmal" || Mnemonic == "vfmsl" || - Mnemonic == "sb") { + Mnemonic == "sb" || Mnemonic == "ssbb" || + Mnemonic == "pssbb") { // These mnemonics are never predicable CanAcceptPredicationCode = false; } else if (!isThumb()) { @@ -6824,6 +6825,26 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst, "code specified"); break; } + case ARM::DSB: + case ARM::t2DSB: { + + if (Inst.getNumOperands() < 2) + break; + + unsigned Option = Inst.getOperand(0).getImm(); + unsigned Pred = Inst.getOperand(1).getImm(); + + // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL). + if (Option == 0 && Pred != ARMCC::AL) + return Error(Operands[1]->getStartLoc(), + "instruction 'ssbb' is not predicable, but condition code " + "specified"); + if (Option == 4 && Pred != ARMCC::AL) + return Error(Operands[1]->getStartLoc(), + "instruction 'pssbb' is not predicable, but condition code " + "specified"); + break; + } case ARM::VMOVRRS: { // Source registers must be sequential. const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); |
