1 files changed, 16 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index dcb64c5131c..ef42bd20caf 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -22,6 +22,10 @@
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
+static cl::opt<bool>
+LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
+            cl::desc("Move ld / st multiple pass before postalloc scheduling"));
+
 static const MCAsmInfo *createMCAsmInfo(const Target &T,
                                         const StringRef &TT) {
   Triple TheTriple(TT);
@@ -101,11 +105,22 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
   return true;
 }
 
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
+                                        CodeGenOpt::Level OptLevel) {
+  // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+  if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+    if (LdStBeforeSched)
+      PM.add(createARMLoadStoreOptimizationPass());
+
+  return true;
+}
+
 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
                                           CodeGenOpt::Level OptLevel) {
   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
-    PM.add(createARMLoadStoreOptimizationPass());
+    if (!LdStBeforeSched)
+      PM.add(createARMLoadStoreOptimizationPass());
     PM.add(createIfConverterPass());
   }