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-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.h5
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index ad0b1bb5dee..8478665979f 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -223,9 +223,6 @@ protected:
/// register allocation.
bool DisablePostRAScheduler = false;
- /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
- bool UseAA = false;
-
/// HasThumb2 - True if Thumb2 instructions are supported.
bool HasThumb2 = false;
@@ -811,7 +808,7 @@ public:
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
- bool useAA() const override { return UseAA; }
+ bool useAA() const override { return true; }
// enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override;
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