summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMScheduleA9.td
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/ARM/ARMScheduleA9.td')
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleA9.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td
index 9739ed20ce2..884c780399d 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA9.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA9.td
@@ -2493,4 +2493,11 @@ def : SchedAlias<ReadALUsr, A9ReadALU>;
def : SchedAlias<WriteCMP, A9WriteALU>;
def : SchedAlias<WriteCMPsi, A9WriteALU>;
def : SchedAlias<WriteCMPsr, A9WriteALU>;
+def : WriteRes<WriteDiv, []> { let Latency = 0; }
+
+def : WriteRes<WriteBr, [A9UnitB]>;
+def : WriteRes<WriteBrL, [A9UnitB]>;
+def : WriteRes<WriteBrTbl, [A9UnitB]>;
+def : WriteRes<WritePreLd, []>;
+def : SchedAlias<WriteCvtFP, A9WriteF>;
} // SchedModel = CortexA9Model
OpenPOWER on IntegriCloud