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-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index e171f8b0929..ca3d6d7dace 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -698,7 +698,7 @@ def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
}
// Writeback version is just a pseudo, as there's no encoding difference.
-// Writeback happens iff the base register is not in the destination register
+// Writeback happens if the base register is not in the destination register
// list.
def tLDMIA_UPD :
InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
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