diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 284 |
1 files changed, 146 insertions, 138 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 2577555246f..914be0390b4 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -73,7 +73,7 @@ def thumb_immshifted_shamt : SDNodeXForm<imm, [{ def t_addrmode_rr : Operand<i32>, ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { let PrintMethod = "printThumbAddrModeRROperand"; - let MIOperandInfo = (ops GPR:$base, GPR:$offsreg); + let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); } // t_addrmode_s4 := reg + reg @@ -82,7 +82,7 @@ def t_addrmode_rr : Operand<i32>, def t_addrmode_s4 : Operand<i32>, ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> { let PrintMethod = "printThumbAddrModeS4Operand"; - let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg); + let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); } // t_addrmode_s2 := reg + reg @@ -91,7 +91,7 @@ def t_addrmode_s4 : Operand<i32>, def t_addrmode_s2 : Operand<i32>, ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> { let PrintMethod = "printThumbAddrModeS2Operand"; - let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg); + let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); } // t_addrmode_s1 := reg + reg @@ -100,7 +100,7 @@ def t_addrmode_s2 : Operand<i32>, def t_addrmode_s1 : Operand<i32>, ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> { let PrintMethod = "printThumbAddrModeS1Operand"; - let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg); + let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); } // t_addrmode_sp := sp + imm8 * 4 @@ -108,7 +108,7 @@ def t_addrmode_s1 : Operand<i32>, def t_addrmode_sp : Operand<i32>, ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { let PrintMethod = "printThumbAddrModeSPOperand"; - let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); + let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); } //===----------------------------------------------------------------------===// @@ -128,9 +128,9 @@ PseudoInst<(outs), (ins i32imm:$amt), } let isNotDuplicable = 1 in -def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), +def tPICADD : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp), "$cp:\n\tadd $dst, pc", - [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; + [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>; //===----------------------------------------------------------------------===// // Control Flow Instructions. @@ -139,7 +139,7 @@ def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), let isReturn = 1, isTerminator = 1 in { def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>; // Alternative return instruction used by vararg functions. - def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>; + def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>; } // FIXME: remove when we have a way to marking a MI with these properties. @@ -157,13 +157,13 @@ let isCall = 1, def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), "blx ${func:call}", [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>; - def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), + def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops), "blx $func", - [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>; + [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>; // ARMv4T - def tBX : TIx2<(outs), (ins GPR:$func, variable_ops), + def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), "cpy lr, pc\n\tbx $func", - [(ARMcall_nolink GPR:$func)]>; + [(ARMcall_nolink tGPR:$func)]>; } let isBranch = 1, isTerminator = 1 in { @@ -176,9 +176,9 @@ let isBranch = 1, isTerminator = 1 in { def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>; def tBR_JTr : TJTI<(outs), - (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), "cpy pc, $target \n\t.align\t2\n$jt", - [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; + [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>; } } @@ -193,68 +193,68 @@ let isBranch = 1, isTerminator = 1 in // let canFoldAsLoad = 1 in -def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr), +def tLDR : TI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), "ldr $dst, $addr", - [(set GPR:$dst, (load t_addrmode_s4:$addr))]>; + [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>; -def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr), +def tLDRB : TI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), "ldrb $dst, $addr", - [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>; + [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>; -def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr), +def tLDRH : TI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), "ldrh $dst, $addr", - [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>; + [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>; -def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr), +def tLDRSB : TI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), "ldrsb $dst, $addr", - [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; + [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; -def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr), +def tLDRSH : TI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), "ldrsh $dst, $addr", - [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; + [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; let canFoldAsLoad = 1 in -def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), +def tLDRspi : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", - [(set GPR:$dst, (load t_addrmode_sp:$addr))]>; + [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>; // Special instruction for restore. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). let canFoldAsLoad = 1, mayLoad = 1 in -def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr), +def tRestore : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), "ldr $dst, $addr", []>; // Load tconstpool let canFoldAsLoad = 1 in -def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr), +def tLDRpci : TIs<(outs tGPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", - [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; + [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; // Special LDR for loads from non-pc-relative constpools. let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in -def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), +def tLDRcp : TIs<(outs tGPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; -def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), +def tSTR : TI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), "str $src, $addr", - [(store GPR:$src, t_addrmode_s4:$addr)]>; + [(store tGPR:$src, t_addrmode_s4:$addr)]>; -def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr), +def tSTRB : TI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), "strb $src, $addr", - [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>; + [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>; -def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr), +def tSTRH : TI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), "strh $src, $addr", - [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>; + [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>; -def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), +def tSTRspi : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), "str $src, $addr", - [(store GPR:$src, t_addrmode_sp:$addr)]>; + [(store tGPR:$src, t_addrmode_sp:$addr)]>; let mayStore = 1 in { // Special instruction for spill. It cannot clobber condition register // when it's expanded by eliminateCallFramePseudoInstr(). -def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr), +def tSpill : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), "str $src, $addr", []>; } @@ -277,205 +277,213 @@ def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops), // // Add with carry -def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tADC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "adc $dst, $rhs", - [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>; -def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tADDS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "add $dst, $lhs, $rhs", - [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>; -def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tADDi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $lhs, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>; + [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>; -def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tADDi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>; + [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>; -def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tADDrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "add $dst, $lhs, $rhs", - [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>; -def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), - "add $dst, $rhs", []>; +def tADDhirr : TIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), + "add $dst, $rhs @ addhirr", []>; -def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs), +def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs), "add $dst, pc, $rhs * 4", []>; -def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs), - "add $dst, $sp, $rhs * 4", []>; -def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), + +def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), + "add $dst, $sp, $rhs * 4 @ addrspi", []>; + +def tADDspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "add $dst, $rhs * 4", []>; -def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "and $dst, $rhs", - [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>; -def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tASRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "asr $dst, $lhs, $rhs", - [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (sra tGPR:$lhs, imm:$rhs))]>; -def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tASRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "asr $dst, $rhs", - [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>; -def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tBIC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "bic $dst, $rhs", - [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>; + [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>; -def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs), +def tCMN : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", - [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>; + [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; -def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs), +def tCMPi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", - [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>; + [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>; -def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs), +def tCMPr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmp $lhs, $rhs", - [(ARMcmp GPR:$lhs, GPR:$rhs)]>; + [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>; -def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs), +def tTST : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), "tst $lhs, $rhs", - [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>; + [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>; -def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs), +def tCMNNZ : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmn $lhs, $rhs", - [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>; + [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>; -def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs), +def tCMPNZi8 : TI<(outs), (ins tGPR:$lhs, i32imm:$rhs), "cmp $lhs, $rhs", - [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>; + [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>; -def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs), +def tCMPNZr : TI<(outs), (ins tGPR:$lhs, tGPR:$rhs), "cmp $lhs, $rhs", - [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>; + [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>; // TODO: A7-37: CMP(3) - cmp hi regs -def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tEOR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "eor $dst, $rhs", - [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>; -def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tLSLri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsl $dst, $lhs, $rhs", - [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (shl tGPR:$lhs, imm:$rhs))]>; -def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tLSLrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsl $dst, $rhs", - [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>; -def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tLSRri : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "lsr $dst, $lhs, $rhs", - [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>; + [(set tGPR:$dst, (srl tGPR:$lhs, imm:$rhs))]>; -def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tLSRrr : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "lsr $dst, $rhs", - [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>; // FIXME: This is not rematerializable because mov changes the condition code. -def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src), +def tMOVi8 : TI<(outs tGPR:$dst), (ins i32imm:$src), "mov $dst, $src", - [(set GPR:$dst, imm0_255:$src)]>; + [(set tGPR:$dst, imm0_255:$src)]>; // TODO: A7-73: MOV(2) - mov setting flag. // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy', // which is MOV(3). This also supports high registers. -def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src), - "cpy $dst, $src", []>; - -def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tMOVr : TI<(outs tGPR:$dst), (ins tGPR:$src), + "cpy $dst, $src", []>; +def tMOVhir2lor : TI<(outs tGPR:$dst), (ins GPR:$src), + "cpy $dst, $src\t@ hir2lor", []>; +def tMOVlor2hir : TI<(outs GPR:$dst), (ins tGPR:$src), + "cpy $dst, $src\t@ lor2hir", []>; +def tMOVhir2hir : TI<(outs GPR:$dst), (ins GPR:$src), + "cpy $dst, $src\t@ hir2hir", []>; + +def tMUL : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "mul $dst, $rhs", - [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>; -def tMVN : TI<(outs GPR:$dst), (ins GPR:$src), +def tMVN : TI<(outs tGPR:$dst), (ins tGPR:$src), "mvn $dst, $src", - [(set GPR:$dst, (not GPR:$src))]>; + [(set tGPR:$dst, (not tGPR:$src))]>; -def tNEG : TI<(outs GPR:$dst), (ins GPR:$src), +def tNEG : TI<(outs tGPR:$dst), (ins tGPR:$src), "neg $dst, $src", - [(set GPR:$dst, (ineg GPR:$src))]>; + [(set tGPR:$dst, (ineg tGPR:$src))]>; -def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tORR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "orr $dst, $rhs", - [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>; -def tREV : TI<(outs GPR:$dst), (ins GPR:$src), +def tREV : TI<(outs tGPR:$dst), (ins tGPR:$src), "rev $dst, $src", - [(set GPR:$dst, (bswap GPR:$src))]>, + [(set tGPR:$dst, (bswap tGPR:$src))]>, Requires<[IsThumb, HasV6]>; -def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src), +def tREV16 : TI<(outs tGPR:$dst), (ins tGPR:$src), "rev16 $dst, $src", - [(set GPR:$dst, - (or (and (srl GPR:$src, 8), 0xFF), - (or (and (shl GPR:$src, 8), 0xFF00), - (or (and (srl GPR:$src, 8), 0xFF0000), - (and (shl GPR:$src, 8), 0xFF000000)))))]>, + [(set tGPR:$dst, + (or (and (srl tGPR:$src, 8), 0xFF), + (or (and (shl tGPR:$src, 8), 0xFF00), + (or (and (srl tGPR:$src, 8), 0xFF0000), + (and (shl tGPR:$src, 8), 0xFF000000)))))]>, Requires<[IsThumb, HasV6]>; -def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src), +def tREVSH : TI<(outs tGPR:$dst), (ins tGPR:$src), "revsh $dst, $src", - [(set GPR:$dst, + [(set tGPR:$dst, (sext_inreg - (or (srl (and GPR:$src, 0xFFFF), 8), - (shl GPR:$src, 8)), i16))]>, + (or (srl (and tGPR:$src, 0xFFFF), 8), + (shl tGPR:$src, 8)), i16))]>, Requires<[IsThumb, HasV6]>; -def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tROR : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "ror $dst, $rhs", - [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>; // Subtract with carry -def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tSBC : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sbc $dst, $rhs", - [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>; -def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tSUBS : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sub $dst, $lhs, $rhs", - [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>; // TODO: A7-96: STMIA - store multiple. -def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tSUBi3 : TI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $lhs, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>; + [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>; -def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tSUBi8 : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs", - [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>; + [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>; -def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), +def tSUBrr : TI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), "sub $dst, $lhs, $rhs", - [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>; + [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>; -def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), +def tSUBspi : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), "sub $dst, $rhs * 4", []>; -def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src), +def tSXTB : TI<(outs tGPR:$dst), (ins tGPR:$src), "sxtb $dst, $src", - [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>, + [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, Requires<[IsThumb, HasV6]>; -def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src), +def tSXTH : TI<(outs tGPR:$dst), (ins tGPR:$src), "sxth $dst, $src", - [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>, + [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, Requires<[IsThumb, HasV6]>; -def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src), +def tUXTB : TI<(outs tGPR:$dst), (ins tGPR:$src), "uxtb $dst, $src", - [(set GPR:$dst, (and GPR:$src, 0xFF))]>, + [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, Requires<[IsThumb, HasV6]>; -def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src), +def tUXTH : TI<(outs tGPR:$dst), (ins tGPR:$src), "uxth $dst, $src", - [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>, + [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, Requires<[IsThumb, HasV6]>; @@ -483,20 +491,20 @@ def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src), // Expanded by the scheduler into a branch sequence. let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. def tMOVCCr : - PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc), + PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), "@ tMOVCCr $cc", - [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>; + [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. -def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label), +def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label), !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", "${:private}PCRELL${:uid}+4))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", "${:private}PCRELL${:uid}:\n\tadd $dst, pc")), []>; -def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id), +def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", "${:private}PCRELL${:uid}+4))\n"), !strconcat("\tmov $dst, #PCRELV${:uid}\n", @@ -532,7 +540,7 @@ def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>; def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>; // Indirect calls to ARM routines -def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>; +def : ThumbV5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>; // zextload i1 -> zextload i8 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr), |
