diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrNEON.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 6f3f6a0f0f8..24563a1a5e2 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -169,7 +169,7 @@ class VLD1D<bits<4> op7_4, string Dt> "vld1", Dt, "\\{$dst\\}, $addr", "", []>; class VLD1Q<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2), - (ins addrmode6:$addr), IIC_VLD2, + (ins addrmode6:$addr), IIC_VLD1x2, "vld1", Dt, "\\{$dst1, $dst2\\}, $addr", "", []>; def VLD1d8 : VLD1D<0b0000, "8">; @@ -182,20 +182,20 @@ def VLD1q16 : VLD1Q<0b0100, "16">; def VLD1q32 : VLD1Q<0b1000, "32">; def VLD1q64 : VLD1Q<0b1100, "64">; -def VLD1q8Pseudo : VLDQPseudo<IIC_VLD2>; -def VLD1q16Pseudo : VLDQPseudo<IIC_VLD2>; -def VLD1q32Pseudo : VLDQPseudo<IIC_VLD2>; -def VLD1q64Pseudo : VLDQPseudo<IIC_VLD2>; +def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>; +def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>; +def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>; +def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>; // ...with address register writeback: class VLD1DWB<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1u, "vld1", Dt, "\\{$dst\\}, $addr$offset", "$addr.addr = $wb", []>; class VLD1QWB<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x2u, "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", "$addr.addr = $wb", []>; @@ -209,19 +209,19 @@ def VLD1q16_UPD : VLD1QWB<0b0100, "16">; def VLD1q32_UPD : VLD1QWB<0b1000, "32">; def VLD1q64_UPD : VLD1QWB<0b1100, "64">; -def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; -def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; -def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; -def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; +def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>; +def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>; +def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>; +def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>; // ...with 3 registers (some of these are only for the disassembler): class VLD1D3<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), - (ins addrmode6:$addr), IIC_VLD3, "vld1", Dt, + (ins addrmode6:$addr), IIC_VLD1x3, "vld1", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr", "", []>; class VLD1D3WB<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3, "vld1", Dt, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD1x3u, "vld1", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>; def VLD1d8T : VLD1D3<0b0000, "8">; @@ -234,13 +234,13 @@ def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">; def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">; def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">; -def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD3>; -def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD3>; +def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>; +def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>; // ...with 4 registers (some of these are only for the disassembler): class VLD1D4<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD4, "vld1", Dt, + (ins addrmode6:$addr), IIC_VLD1x4, "vld1", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; class VLD1D4WB<bits<4> op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4, @@ -259,8 +259,8 @@ def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">; def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">; def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">; -def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD4>; -def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD4>; +def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>; +def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>; // VLD2 : Vector Load (multiple 2-element structures) class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt> @@ -270,7 +270,7 @@ class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt> class VLD2Q<bits<4> op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), - (ins addrmode6:$addr), IIC_VLD4, + (ins addrmode6:$addr), IIC_VLD2x2, "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>; def VLD2d8 : VLD2D<0b1000, 0b0000, "8">; @@ -285,20 +285,20 @@ def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>; def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>; def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>; -def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD4>; -def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD4>; -def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD4>; +def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>; +def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>; +def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>; // ...with address register writeback: class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2u, "vld2", Dt, "\\{$dst1, $dst2\\}, $addr$offset", "$addr.addr = $wb", []>; class VLD2QWB<bits<4> op7_4, string Dt> : NLdSt<0, 0b10, 0b0011, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2x2u, "vld2", Dt, "\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb", []>; @@ -310,13 +310,13 @@ def VLD2q8_UPD : VLD2QWB<0b0000, "8">; def VLD2q16_UPD : VLD2QWB<0b0100, "16">; def VLD2q32_UPD : VLD2QWB<0b1000, "32">; -def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; -def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; -def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2>; +def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>; +def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>; +def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>; -def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>; -def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>; -def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4>; +def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>; +def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>; +def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>; // ...with double-spaced registers (for disassembly only): def VLD2b8 : VLD2D<0b1001, 0b0000, "8">; @@ -455,29 +455,29 @@ class VLDQQQQLNWBPseudo<InstrItinClass itin> class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane), - IIC_VLD2, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr", + IIC_VLD2ln, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr", "$src1 = $dst1, $src2 = $dst2", []>; def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8">; def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16">; def VLD2LNd32 : VLD2LN<0b1001, {?,0,?,?}, "32">; -def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2>; -def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2>; -def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2>; +def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>; +def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>; +def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>; // ...with double-spaced registers: def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16">; def VLD2LNq32 : VLD2LN<0b1001, {?,1,?,?}, "32">; -def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2>; -def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2>; +def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; +def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; // ...with address register writeback: class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> : NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset, - DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2, "vld2", Dt, + DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, "\\{$dst1[$lane], $dst2[$lane]\\}, $addr$offset", "$src1 = $dst1, $src2 = $dst2, $addr.addr = $wb", []>; @@ -485,15 +485,15 @@ def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8">; def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16">; def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,?,?}, "32">; -def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>; -def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>; -def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2>; +def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; +def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; +def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16">; def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,?,?}, "32">; -def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>; -def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2>; +def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; +def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; // VLD3LN : Vector Load (single 3-element structure to one lane) class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
