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-rw-r--r--llvm/lib/Target/ARM/ARMInstrFormats.td134
1 files changed, 0 insertions, 134 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 50bb9af71da..e79608d360c 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -1495,32 +1495,6 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
let D = VFPNeonDomain;
}
-class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
- InstrItinClass itin,
- string opc, string asm, list<dag> pattern>
- : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
- VFPLdStFrm, itin, opc, asm, "", pattern> {
- list<Predicate> Predicates = [HasFullFP16];
-
- // Instruction operands.
- bits<5> Sd;
- bits<13> addr;
-
- // Encode instruction operands.
- let Inst{23} = addr{8}; // U (add = (U == '1'))
- let Inst{22} = Sd{0};
- let Inst{19-16} = addr{12-9}; // Rn
- let Inst{15-12} = Sd{4-1};
- let Inst{7-0} = addr{7-0}; // imm8
-
- let Inst{27-24} = opcod1;
- let Inst{21-20} = opcod2;
- let Inst{11-8} = 0b1001; // Half precision
-
- // Loads & stores operate on both NEON and VFP pipelines.
- let D = VFPNeonDomain;
-}
-
// VFP Load / store multiple pseudo instructions.
class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
list<dag> pattern>
@@ -1843,114 +1817,6 @@ class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
let Inst{22} = Sd{0};
}
-// Half precision, unary, predicated
-class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
- bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
- string asm, list<dag> pattern>
- : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
- list<Predicate> Predicates = [HasFullFP16];
-
- // Instruction operands.
- bits<5> Sd;
- bits<5> Sm;
-
- // Encode instruction operands.
- let Inst{3-0} = Sm{4-1};
- let Inst{5} = Sm{0};
- let Inst{15-12} = Sd{4-1};
- let Inst{22} = Sd{0};
-
- let Inst{27-23} = opcod1;
- let Inst{21-20} = opcod2;
- let Inst{19-16} = opcod3;
- let Inst{11-8} = 0b1001; // Half precision
- let Inst{7-6} = opcod4;
- let Inst{4} = opcod5;
-}
-
-// Half precision, unary, non-predicated
-class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
- bit opcod5, dag oops, dag iops, InstrItinClass itin,
- string asm, list<dag> pattern>
- : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
- VFPUnaryFrm, itin, asm, "", pattern> {
- list<Predicate> Predicates = [HasFullFP16];
-
- // Instruction operands.
- bits<5> Sd;
- bits<5> Sm;
-
- let Inst{31-28} = 0b1111;
-
- // Encode instruction operands.
- let Inst{3-0} = Sm{4-1};
- let Inst{5} = Sm{0};
- let Inst{15-12} = Sd{4-1};
- let Inst{22} = Sd{0};
-
- let Inst{27-23} = opcod1;
- let Inst{21-20} = opcod2;
- let Inst{19-16} = opcod3;
- let Inst{11-8} = 0b1001; // Half precision
- let Inst{7-6} = opcod4;
- let Inst{4} = opcod5;
-}
-
-// Half precision, binary
-class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
- InstrItinClass itin, string opc, string asm, list<dag> pattern>
- : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
- list<Predicate> Predicates = [HasFullFP16];
-
- // Instruction operands.
- bits<5> Sd;
- bits<5> Sn;
- bits<5> Sm;
-
- // Encode instruction operands.
- let Inst{3-0} = Sm{4-1};
- let Inst{5} = Sm{0};
- let Inst{19-16} = Sn{4-1};
- let Inst{7} = Sn{0};
- let Inst{15-12} = Sd{4-1};
- let Inst{22} = Sd{0};
-
- let Inst{27-23} = opcod1;
- let Inst{21-20} = opcod2;
- let Inst{11-8} = 0b1001; // Half precision
- let Inst{6} = op6;
- let Inst{4} = op4;
-}
-
-// Half precision, binary, not predicated
-class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
- InstrItinClass itin, string asm, list<dag> pattern>
- : VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
- VFPBinaryFrm, itin, asm, "", pattern> {
- list<Predicate> Predicates = [HasFullFP16];
-
- // Instruction operands.
- bits<5> Sd;
- bits<5> Sn;
- bits<5> Sm;
-
- let Inst{31-28} = 0b1111;
-
- // Encode instruction operands.
- let Inst{3-0} = Sm{4-1};
- let Inst{5} = Sm{0};
- let Inst{19-16} = Sn{4-1};
- let Inst{7} = Sn{0};
- let Inst{15-12} = Sd{4-1};
- let Inst{22} = Sd{0};
-
- let Inst{27-23} = opcod1;
- let Inst{21-20} = opcod2;
- let Inst{11-8} = 0b1001; // Half precision
- let Inst{6} = opcod3;
- let Inst{4} = 0;
-}
-
// VFP conversion instructions
class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
dag oops, dag iops, InstrItinClass itin, string opc, string asm,
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