diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMAsmPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index b636d47df48..41f4d821134 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -137,8 +137,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, assert(!MO.getSubReg() && "Subregs should be eliminated!"); if(ARM::GPRPairRegClass.contains(Reg)) { const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); Reg = TRI->getSubReg(Reg, ARM::gsub_0); } O << ARMInstPrinter::getRegisterName(Reg); @@ -231,8 +230,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'y': // Print a VFP single precision register as indexed double. if (MI->getOperand(OpNum).isReg()) { unsigned Reg = MI->getOperand(OpNum).getReg(); - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); // Find the 'd' register that has this 's' register as a sub-register, // and determine the lane number. for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { @@ -264,8 +262,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, // inline asm statement. O << "{"; if (ARM::GPRPairRegClass.contains(RegBegin)) { - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); O << ARMInstPrinter::getRegisterName(Reg0) << ", "; RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); @@ -321,8 +318,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const MachineOperand &MO = MI->getOperand(OpNum); if (!MO.isReg()) return true; - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? ARM::gsub_0 : ARM::gsub_1); O << ARMInstPrinter::getRegisterName(Reg); @@ -348,8 +344,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned Reg = MI->getOperand(OpNum).getReg(); if (!ARM::QPRRegClass.contains(Reg)) return true; - const TargetRegisterInfo *TRI = - MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); O << ARMInstPrinter::getRegisterName(SubReg); @@ -364,8 +359,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, if (!MO.isReg()) return true; const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *TRI = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); unsigned Reg = MO.getReg(); if(!ARM::GPRPairRegClass.contains(Reg)) return false; @@ -1035,8 +1029,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { MCTargetStreamer &TS = *OutStreamer.getTargetStreamer(); ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS); const MachineFunction &MF = *MI->getParent()->getParent(); - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>(); unsigned FramePtr = RegInfo->getFrameRegister(MF); |
