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-rw-r--r--llvm/lib/Target/ARC/ARCInstrFormats.td431
1 files changed, 407 insertions, 24 deletions
diff --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td
index 94240e90a60..bddef6b9500 100644
--- a/llvm/lib/Target/ARC/ARCInstrFormats.td
+++ b/llvm/lib/Target/ARC/ARCInstrFormats.td
@@ -17,18 +17,23 @@ class Encoding64 {
}
// Address operands
-def immU6 : Operand<i32>, PatLeaf<(imm), [{
- return isUInt<6>(N->getSExtValue()); }]> {
+
+class immU<int BSz> : Operand<i32>, PatLeaf<(imm),
+ "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
}
-def immS12 : Operand<i32>, PatLeaf<(imm), [{
- return isInt<12>(N->getSExtValue()); }]> {
- let DecoderMethod = "DecodeS12Operand";
+def immU6 : immU<6>;
+
+class immS<int BSz> : Operand<i32>, PatLeaf<(imm),
+ "\n return isInt<"#BSz#">(N->getSExtValue());"> {
+ let DecoderMethod = "DecodeSignedOperand<"#BSz#">";
}
-def immS9 : Operand<i32>, PatLeaf<(imm), [{
- return isInt<9>(N->getSExtValue()); }]> {
- let DecoderMethod = "DecodeS9Operand";
+// e.g. s3 field may encode the signed integers values -1 .. 6
+// using binary codes 111, 000, 001, 010, 011, 100, 101, and 110, respectively
+class immC<int BSz> : Operand<i32>, PatLeaf<(imm),
+ "\n return isInt<"#BSz#">(N->getSExtValue());"> {
+ let DecoderMethod = "DecodeFromCyclicRange<"#BSz#">";
}
def MEMii : Operand<i32> {
@@ -36,7 +41,7 @@ def MEMii : Operand<i32> {
}
def MEMrs9 : Operand<iAny> {
- let MIOperandInfo = (ops GPR32:$B, immS9:$S9);
+ let MIOperandInfo = (ops GPR32:$B, immS<9>:$S9);
let PrintMethod = "printMemOperandRI";
let DecoderMethod = "DecodeMEMrs9";
}
@@ -47,6 +52,10 @@ def MEMrlimm : Operand<iAny> {
let DecoderMethod = "DecodeMEMrlimm";
}
+def GPR32Reduced : Operand<iAny> {
+ let DecoderMethod = "DecodeGBR32ShortRegister";
+}
+
class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction, Encoding64 {
@@ -153,7 +162,6 @@ class F32_BR1_BL_COND<dag outs, dag ins, string asmstr, list<dag> pat> :
let Inst{17} = 0;
}
-
// BRcc targets have limited 9-bit range. These are for compare and branch
// in single instruction. Their targets are 2-byte aligned. They also use
// a different (3-bit) set of condition codes.
@@ -464,6 +472,342 @@ class F32_ST_LIMM<bit di, bits<2> zz, dag outs, dag ins,
let DecoderMethod = "DecodeStLImmInstruction";
}
+// Compact Move/Load.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// | |h | |i|H |
+class F16_COMPACT<bits<1> i, dag outs, dag ins,
+ string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<5> h;
+
+ let Inst{15-11} = 0b01000;
+ let Inst{7-5} = h{2-0};
+ let Inst{2} = i;
+ let Inst{1-0} = h{4-3};
+}
+
+// Compact Load/Add/Sub.
+class F16_LD_ADD_SUB<dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<3> b;
+ let Inst{15-11} = 0b01001;
+ let Inst{10-8} = b;
+}
+
+class F16_LD_SUB<bit i, string asmstr> :
+ F16_LD_ADD_SUB<(outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
+ asmstr> {
+
+ bits<3> a;
+ bits<3> c;
+
+ let Inst{7-5} = c;
+ let Inst{4} = i;
+ let Inst{3} = 0;
+ let Inst{2-0} = a;
+}
+
+class F16_ADD :
+ F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6),
+ "add_s\t$r, $b, $u6"> {
+
+ bit r;
+ bits<6> u6;
+
+ let Inst{7} = r;
+ let Inst{6-4} = u6{5-3};
+ let Inst{3} = 1;
+ let Inst{2-0} = u6{2-0};
+}
+
+// Compact Load/Store.
+class F16_LD_ST_1<dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ let Inst{15-11} = 0b01010;
+}
+
+class F16_LD_ST_s11<bit i, string asmstr> :
+ F16_LD_ST_1<(outs), (ins immS<11>:$s11), asmstr> {
+
+ bits<11> s11;
+
+ let Inst{10-5} = s11{10-5};
+ let Inst{4} = i;
+ let Inst{3} = 0;
+ let Inst{2-0} = s11{4-2};
+ let s11{1-0} = 0b00;
+}
+
+class F16_LDI_u7 :
+ F16_LD_ST_1<(outs GPR32:$b), (ins immU<7>:$u7),
+ "ldi_s\t$b, [$u7]"> {
+
+ bits<3> b;
+ bits<7> u7;
+
+ let Inst{10-8} = b;
+ let Inst{7-4} = u7{6-3};
+ let Inst{3} = 1;
+ let Inst{2-0} = u7{2-0};
+}
+
+// Indexed Jump or Execute.
+class F16_JLI_EI<bit i, string asmstr> :
+ InstARC<2, (outs), (ins immU<10>:$u10),
+ !strconcat(asmstr, "\t$u10"), []> {
+
+ bits<10> u10;
+
+ let Inst{15-11} = 0b01011;
+ let Inst{10} = i;
+ let Inst{9-0} = u10;
+}
+
+// Load/Add Register-Register.
+class F16_LD_ADD_RR<bits<2> i, string asmstr> :
+ InstARC<2, (outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
+ asmstr, []> {
+
+ bits<3> a;
+ bits<3> b;
+ bits<3> c;
+
+ let Inst{15-11} = 0b01100;
+ let Inst{10-8} = b;
+ let Inst{7-5} = c;
+ let Inst{4-3} = i;
+ let Inst{2-0} = a;
+}
+
+// Load/Add GP-Relative.
+class F16_GP_LD_ADD<bits<2> i, dag ins, string asmstr> :
+ InstARC<2, (outs), ins, asmstr, []> {
+
+ let Inst{15-11} = 0b11001;
+ let Inst{10-9} = i;
+}
+
+// Add/Sub/Shift Register-Immediate.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b |c |i |u |
+class F16_ADD_IMM<bits<2> i, string asmstr> :
+ InstARC<2, (outs GPR32:$c), (ins GPR32:$b, immU<3>:$u3),
+ !strconcat(asmstr, "\t$c, $b, $u3"), []> {
+
+ bits<3> b;
+ bits<3> c;
+ bits<3> u3;
+
+ let Inst{15-11} = 0b01101;
+ let Inst{10-8} = b;
+ let Inst{7-5} = c;
+ let Inst{4-3} = i;
+ let Inst{2-0} = u3;
+}
+
+// Dual Register Operations.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b/s |h |i |H |
+class F16_OP_HREG<bits<3> i, dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<3> b_s3;
+ bits<5> h;
+
+ let Inst{15-11} = 0b01110;
+ let Inst{10-8} = b_s3;
+ let Inst{7-5} = h{2-0};
+ let Inst{4-2} = i;
+ let Inst{1-0} = h{4-3};
+}
+
+class F16_OP_HREG30<bits<3> i, dag outs, dag ins, string asmstr> :
+ F16_OP_HREG<i, outs, ins, asmstr> {
+
+ bits<5> LImmReg = 0b11110;
+ let Inst{7-5} = LImmReg{2-0};
+ let Inst{1-0} = LImmReg{4-3};
+}
+
+class F16_OP_HREG_LIMM<bits<3> i, dag outs, dag ins, string asmstr> :
+ F16_OP_HREG30<i, outs, ins, asmstr> {
+
+ bits<32> LImm;
+ let Inst{47-16} = LImm;
+ let Size = 6;
+}
+
+// General compact DOP format.
+class F16_GEN_DOP_BASE<bits<5> i, dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<3> b;
+ bits<3> c;
+ let Inst{15-11} = 0b01111;
+ let Inst{10-8} = b;
+ let Inst{7-5} = c;
+ let Inst{4-0} = i;
+}
+
+class F16_GEN_DOP<bits<5> i, string asmstr> :
+ F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
+ !strconcat(asmstr, "\t$b, $b, $c")>;
+
+class F16_GEN_DOP_NODST<bits<5> i, string asmstr> :
+ F16_GEN_DOP_BASE<i, (outs), (ins GPR32:$b, GPR32:$c),
+ !strconcat(asmstr, "\t$b, $c")>;
+
+class F16_GEN_DOP_SINGLESRC<bits<5> i, string asmstr> :
+ F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
+ !strconcat(asmstr, "\t$b, $c")>;
+
+class F16_GEN_SOP_BASE<bits<3> i, dag outs, dag ins, string asmstr> :
+ F16_GEN_DOP_BASE<0b00000, outs, ins, asmstr> {
+
+ let c = i;
+}
+
+class F16_GEN_SOP<bits<3> i, string asmstr> :
+ F16_GEN_SOP_BASE<i, (outs), (ins GPR32:$b), asmstr>;
+
+class F16_GEN_ZOP<bits<3> i, string asmstr> :
+ F16_GEN_SOP_BASE<0b111, (outs), (ins), asmstr> {
+
+ let b = i;
+}
+
+// Compact Load/Store with Offset Format.
+class F16_LD_ST_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> {
+
+ bits<3> b;
+ bits<3> c;
+ let Inst{15-11} = opc;
+ let Inst{10-8} = b;
+ let Inst{7-5} = c;
+}
+
+class F16_LD_ST_WORD_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+ F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+ bits<7> off;
+ let Inst{4-0} = off{6-2};
+ let off{1-0} = 0b00;
+}
+
+class F16_LD_ST_HALF_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+ F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+ bits<6> off;
+ let Inst{4-0} = off{5-1};
+ let off{0} = 0b0;
+}
+
+class F16_LD_ST_BYTE_OFF<bits<5> opc, dag outs, dag ins, string asmstr> :
+ F16_LD_ST_OFF<opc, outs, ins, asmstr> {
+
+ bits<5> off;
+ let Inst{4-0} = off;
+}
+
+// Shift/Subtract/Bit Immediate.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b |i |u |
+class F16_SH_SUB_BIT<bits<3> i, string asmstr> :
+ InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> {
+
+ bits<3> b;
+ bits<5> u5;
+
+ let Inst{15-11} = 0b10111;
+ let Inst{10-8} = b;
+ let Inst{7-5} = i;
+ let Inst{4-0} = u5;
+}
+
+class F16_SH_SUB_BIT_DST<bits<3> i, string asmstr> :
+ F16_SH_SUB_BIT<i, !strconcat(asmstr, "\t$b, $b, $u5")>;
+
+// 16-bit stack-based operations.
+// |10|9|8|7|6|5|4|3|2|1|0|
+// |b |i |u |
+class F16_SP_OPS<bits<3> i,
+ dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<3> fieldB;
+ bits<5> fieldU;
+
+ let Inst{15-11} = 0b11000;
+ let Inst{10-8} = fieldB;
+ let Inst{7-5} = i;
+ let Inst{4-0} = fieldU;
+}
+
+class F16_SP_OPS_u7_aligned<bits<3> i,
+ dag outs, dag ins, string asmstr> :
+ F16_SP_OPS<i, outs, ins, asmstr> {
+
+ bits<3> b3;
+ bits<7> u7;
+
+ let fieldB = b3;
+ let fieldU = u7{6-2};
+ let u7{1-0} = 0b00;
+}
+
+class F16_SP_OPS_bconst<bits<3> b, string asmop> :
+ F16_SP_OPS_u7_aligned<0b101,
+ (outs), (ins immU<7>:$u7),
+ !strconcat(asmop, "\t%sp, %sp, $u7")> {
+
+ let fieldB = b;
+}
+
+class F16_SP_OPS_uconst<bits<3> i,
+ dag outs, dag ins, string asmop> :
+ F16_SP_OPS_u7_aligned<i, outs, ins,
+ !strconcat(asmop, "\t$b3")> {
+
+ let fieldU = 0b00001;
+}
+
+class F16_SP_OPS_buconst<bits<3> i, string asmop> :
+ F16_SP_OPS_u7_aligned<i, (outs), (ins),
+ !strconcat(asmop, "\t%blink")> {
+
+ let fieldB = 0x000;
+ let fieldU = 0b10001;
+}
+
+class F16_SP_LD<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
+ (outs GPR32Reduced:$b3), (ins immU<7>:$u7),
+ !strconcat(asmop, "\t$b3, [%sp, $u7]")>;
+
+class F16_SP_ST<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
+ (outs), (ins GPR32Reduced:$b3, immU<7>:$u7),
+ !strconcat(asmop, "\t$b3, [%sp, $u7]")>;
+
+// Compact MOV/ADD/CMP Immediate Format.
+class F16_OP_IMM<bits<5> opc, dag outs, dag ins, string asmstr> :
+ InstARC<2, outs, ins, asmstr, []> {
+
+ bits<3> b;
+ let Inst{15-11} = opc;
+ let Inst{10-8} = b;
+}
+
+class F16_OP_U7<bit i, string asmstr> :
+ F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> {
+
+ bits<7> u7;
+ let Inst{7} = i;
+ let Inst{6-0} = u7;
+}
+
// Special types for different instruction operands.
def cmovpred : Operand<i32>, PredicateOp,
ComplexPattern<i32, 2, "SelectCMOVPred"> {
@@ -481,28 +825,67 @@ def brccond : Operand<i32> {
let PrintMethod = "printBRCCPredicateOperand";
}
-// Branch targets of different offset sizes.
-def btarget : Operand<OtherVT> {
+// Branch/call targets of different offset sizes.
+class BCTarget<ValueType vt> : Operand<vt> {
let OperandType = "OPERAND_PCREL";
}
-def btargetS9 : Operand<OtherVT> {
- let OperandType = "OPERAND_PCREL";
- let DecoderMethod = "DecodeBranchTargetS9";
+def btarget : BCTarget<OtherVT>;
+
+class BCTargetSigned<ValueType vt, int BSz> : BCTarget<vt> {
+ let DecoderMethod = "DecodeBranchTargetS<"#BSz#">";
}
-def btargetS21 : Operand<OtherVT> {
- let OperandType = "OPERAND_PCREL";
- let DecoderMethod = "DecodeBranchTargetS21";
+class BranchTargetS<int BSz> : BCTargetSigned<OtherVT, BSz>;
+def btargetS7 : BranchTargetS<7>;
+def btargetS8 : BranchTargetS<8>;
+def btargetS9 : BranchTargetS<9>;
+def btargetS10 : BranchTargetS<10>;
+def btargetS13 : BranchTargetS<13>;
+def btargetS21 : BranchTargetS<21>;
+def btargetS25 : BranchTargetS<25>;
+
+class CallTargetS<int BSz> : BCTargetSigned<i32, BSz>;
+def calltargetS25: CallTargetS<25>;
+
+// Compact Branch on Compare Register with Zero.
+class F16_BCC_REG<bit i, string asmstr> :
+ InstARC<2, (outs), (ins GPR32:$b, btargetS8:$s8),
+ !strconcat(asmstr, "\t$b, 0, $s8"), []> {
+
+ bits<3> b;
+ bits<8> s8;
+
+ let Inst{15-11} = 0b11101;
+ let Inst{10-8} = b;
+ let Inst{7} = i;
+ let Inst{6-0} = s8{7-1};
+ let s8{0} = 0b0;
}
-def btargetS25 : Operand<OtherVT> {
- let OperandType = "OPERAND_PCREL";
- let DecoderMethod = "DecodeBranchTargetS25";
+// Compact Branch Conditionally Format.
+class F16_BCC<bits<2> i, dag ins, string asmstr> :
+ InstARC<2, (outs), ins, asmstr, []> {
+
+ let Inst{15-11} = 0b11110;
+ let Inst{10-9} = i;
}
-def calltargetS25: Operand<i32> {
- let OperandType = "OPERAND_PCREL";
- let DecoderMethod = "DecodeBranchTargetS25";
+class F16_BCC_s10<bits<2> i, string asmstr> :
+ F16_BCC<i, (ins btargetS10:$s),
+ !strconcat(asmstr, "\t$s")> {
+
+ bits<10> s;
+ let Inst{8-0} = s{9-1};
+ let s{0} = 0b0;
}
+class F16_BCC_s7<bits<3> i, string asmstr> :
+ F16_BCC<0b11, (ins btargetS7:$s),
+ !strconcat(asmstr, "\t$s")> {
+
+ bits<7> s;
+ let Inst{8-6} = i;
+ let Inst{5-0} = s{6-1};
+ let s{0} = 0b0;
+}
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