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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp81
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h10
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUPTNote.h26
-rw-r--r--llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp22
-rw-r--r--llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp21
-rw-r--r--llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h9
6 files changed, 79 insertions, 90 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index a5c3745fcdf..1cd570d3c0e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -36,11 +36,13 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
using namespace llvm;
+using namespace llvm::AMDGPU;
// TODO: This should get the default rounding mode from the kernel. We just set
// the default here, but this could change if the OpenCL rounding mode pragmas
@@ -114,7 +116,7 @@ void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits());
if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
- readPalMetadata(M);
+ readPALMetadata(M);
// AMDPAL wants an HSA_ISA .note.
getTargetStreamer().EmitDirectiveHSACodeObjectISA(
ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU");
@@ -132,12 +134,12 @@ void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
if (TM.getTargetTriple().getOS() == Triple::AMDPAL) {
// Copy the PAL metadata from the map where we collected it into a vector,
// then write it as a .note.
- std::vector<uint32_t> Data;
- for (auto i : PalMetadata) {
- Data.push_back(i.first);
- Data.push_back(i.second);
+ PALMD::Metadata PALMetadataVector;
+ for (auto i : PALMetadataMap) {
+ PALMetadataVector.push_back(i.first);
+ PALMetadataVector.push_back(i.second);
}
- getTargetStreamer().EmitPalMetadata(Data);
+ getTargetStreamer().EmitPALMetadata(PALMetadataVector);
}
if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
@@ -207,11 +209,11 @@ bool AMDGPUAsmPrinter::doFinalization(Module &M) {
}
// For the amdpal OS type, read the amdgpu.pal.metadata supplied by the
-// frontend into our PalMetadata map, ready for per-function modification. It
+// frontend into our PALMetadataMap, ready for per-function modification. It
// is a NamedMD containing an MDTuple containing a number of MDNodes each of
// which is an integer value, and each two integer values forms a key=value
-// pair that we store as PalMetadata[key]=value in the map.
-void AMDGPUAsmPrinter::readPalMetadata(Module &M) {
+// pair that we store as PALMetadataMap[key]=value in the map.
+void AMDGPUAsmPrinter::readPALMetadata(Module &M) {
auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
if (!NamedMD || !NamedMD->getNumOperands())
return;
@@ -223,7 +225,7 @@ void AMDGPUAsmPrinter::readPalMetadata(Module &M) {
auto Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1));
if (!Key || !Val)
continue;
- PalMetadata[Key->getZExtValue()] = Val->getZExtValue();
+ PALMetadataMap[Key->getZExtValue()] = Val->getZExtValue();
}
}
@@ -270,7 +272,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
}
if (STM.isAmdPalOS())
- EmitPalMetadata(MF, CurrentProgramInfo);
+ EmitPALMetadata(MF, CurrentProgramInfo);
if (!STM.isAmdHsaOS()) {
EmitProgramInfoSI(MF, CurrentProgramInfo);
}
@@ -964,10 +966,10 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
// is AMDPAL. It stores each compute/SPI register setting and other PAL
-// metadata items into the PalMetadata map, combining with any provided by the
-// frontend as LLVM metadata. Once all functions are written, PalMetadata is
+// metadata items into the PALMetadataMap, combining with any provided by the
+// frontend as LLVM metadata. Once all functions are written, PALMetadataMap is
// then written as a single block in the .note section.
-void AMDGPUAsmPrinter::EmitPalMetadata(const MachineFunction &MF,
+void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
const SIProgramInfo &CurrentProgramInfo) {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// Given the calling convention, calculate the register number for rsrc1. In
@@ -981,52 +983,53 @@ void AMDGPUAsmPrinter::EmitPalMetadata(const MachineFunction &MF,
// Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
// with a constant offset to access any non-register shader-specific PAL
// metadata key.
- unsigned ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE;
+ unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
switch (MF.getFunction()->getCallingConv()) {
case CallingConv::AMDGPU_PS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_VS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::VS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_GS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::GS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_ES:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::ES_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_HS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::HS_SCRATCH_SIZE;
break;
case CallingConv::AMDGPU_LS:
- ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE;
+ ScratchSizeKey = PALMD::Key::LS_SCRATCH_SIZE;
break;
}
- unsigned NumUsedVgprsKey = ScratchSizeKey
- + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS
- - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
- unsigned NumUsedSgprsKey = ScratchSizeKey
- + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS
- - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE;
- PalMetadata[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
- PalMetadata[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
+ unsigned NumUsedVgprsKey = ScratchSizeKey +
+ PALMD::Key::VS_NUM_USED_VGPRS - PALMD::Key::VS_SCRATCH_SIZE;
+ unsigned NumUsedSgprsKey = ScratchSizeKey +
+ PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
+ PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
+ PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
- PalMetadata[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
- PalMetadata[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
+ PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
+ PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
// ScratchSize is in bytes, 16 aligned.
- PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16);
+ PALMetadataMap[ScratchSizeKey] |=
+ alignTo(CurrentProgramInfo.ScratchSize, 16);
} else {
- PalMetadata[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks)
- | S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
+ PALMetadataMap[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
+ S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks);
if (CurrentProgramInfo.ScratchBlocks > 0)
- PalMetadata[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
+ PALMetadataMap[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1);
// ScratchSize is in bytes, 16 aligned.
- PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16);
+ PALMetadataMap[ScratchSizeKey] |=
+ alignTo(CurrentProgramInfo.ScratchSize, 16);
}
if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
- PalMetadata[Rsrc2Reg] |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
- PalMetadata[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
- PalMetadata[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
+ PALMetadataMap[Rsrc2Reg] |=
+ S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
+ PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();
+ PALMetadataMap[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr();
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index abfc6d070f5..fd27d105651 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -112,12 +112,12 @@ private:
SIProgramInfo CurrentProgramInfo;
DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo;
- std::map<uint32_t, uint32_t> PalMetadata;
+ std::map<uint32_t, uint32_t> PALMetadataMap;
uint64_t getFunctionCodeSize(const MachineFunction &MF) const;
SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF) const;
- void readPalMetadata(Module &M);
+ void readPALMetadata(Module &M);
void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF);
void getAmdKernelCode(amd_kernel_code_t &Out, const SIProgramInfo &KernelInfo,
const MachineFunction &MF) const;
@@ -128,8 +128,10 @@ private:
/// \brief Emit register usage information so that the GPU driver
/// can correctly setup the GPU state.
void EmitProgramInfoR600(const MachineFunction &MF);
- void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
- void EmitPalMetadata(const MachineFunction &MF, const SIProgramInfo &KernelInfo);
+ void EmitProgramInfoSI(const MachineFunction &MF,
+ const SIProgramInfo &KernelInfo);
+ void EmitPALMetadata(const MachineFunction &MF,
+ const SIProgramInfo &KernelInfo);
void emitCommonFunctionComments(uint32_t NumVGPR,
uint32_t NumSGPR,
uint32_t ScratchSize,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPTNote.h b/llvm/lib/Target/AMDGPU/AMDGPUPTNote.h
index 6dd0829cf22..de274dfae51 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPTNote.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPTNote.h
@@ -44,32 +44,6 @@ enum NoteType{
NT_AMDGPU_HSA_HLDEBUG_TARGET = 102
};
-enum NoteAmdGpuPalMetadataKey {
- AMDGPU_PAL_METADATA_LS_NUM_USED_VGPRS = 0x10000015,
- AMDGPU_PAL_METADATA_HS_NUM_USED_VGPRS = 0x10000016,
- AMDGPU_PAL_METADATA_ES_NUM_USED_VGPRS = 0x10000017,
- AMDGPU_PAL_METADATA_GS_NUM_USED_VGPRS = 0x10000018,
- AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS = 0x10000019,
- AMDGPU_PAL_METADATA_PS_NUM_USED_VGPRS = 0x1000001a,
- AMDGPU_PAL_METADATA_CS_NUM_USED_VGPRS = 0x1000001b,
-
- AMDGPU_PAL_METADATA_LS_NUM_USED_SGPRS = 0x1000001c,
- AMDGPU_PAL_METADATA_HS_NUM_USED_SGPRS = 0x1000001d,
- AMDGPU_PAL_METADATA_ES_NUM_USED_SGPRS = 0x1000001e,
- AMDGPU_PAL_METADATA_GS_NUM_USED_SGPRS = 0x1000001f,
- AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS = 0x10000020,
- AMDGPU_PAL_METADATA_PS_NUM_USED_SGPRS = 0x10000021,
- AMDGPU_PAL_METADATA_CS_NUM_USED_SGPRS = 0x10000022,
-
- AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE = 0x10000038,
- AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE = 0x10000039,
- AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE = 0x1000003a,
- AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE = 0x1000003b,
- AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE = 0x1000003c,
- AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE = 0x1000003d,
- AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE = 0x1000003e,
-};
-
}
}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4545b9c0d21..046132b7260 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -832,7 +832,9 @@ private:
bool ParseDirectiveAMDKernelCodeT();
bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
bool ParseDirectiveAMDGPUHsaKernel();
- bool ParseDirectivePalMetadata();
+
+ bool ParseDirectivePALMetadata();
+
bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
RegisterKind RegKind, unsigned Reg1,
unsigned RegNum);
@@ -2493,18 +2495,20 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
return false;
}
-bool AMDGPUAsmParser::ParseDirectivePalMetadata() {
- std::vector<uint32_t> Data;
+bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
+ PALMD::Metadata PALMetadata;
for (;;) {
uint32_t Value;
- if (ParseAsAbsoluteExpression(Value))
- return TokError("invalid value in .amdgpu_pal_metadata");
- Data.push_back(Value);
+ if (ParseAsAbsoluteExpression(Value)) {
+ return TokError(Twine("invalid value in ") +
+ Twine(PALMD::AssemblerDirective));
+ }
+ PALMetadata.push_back(Value);
if (getLexer().isNot(AsmToken::Comma))
break;
Lex();
}
- getTargetStreamer().EmitPalMetadata(Data);
+ getTargetStreamer().EmitPALMetadata(PALMetadata);
return false;
}
@@ -2526,8 +2530,8 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
if (IDVal == ".amdgpu_hsa_kernel")
return ParseDirectiveAMDGPUHsaKernel();
- if (IDVal == ".amdgpu_pal_metadata")
- return ParseDirectivePalMetadata();
+ if (IDVal == PALMD::AssemblerDirective)
+ return ParseDirectivePALMetadata();
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index ba5ec180faa..2cbd7932a3b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -112,11 +112,14 @@ bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(StringRef YamlString) {
return true;
}
-bool AMDGPUTargetAsmStreamer::EmitPalMetadata(ArrayRef<uint32_t> Data) {
- OS << "\t.amdgpu_pal_metadata";
- for (auto I = Data.begin(), E = Data.end(); I != E; ++I)
- OS << (I == Data.begin() ? " 0x" : ",0x") << Twine::utohexstr(*I);
- OS << "\n";
+bool AMDGPUTargetAsmStreamer::EmitPALMetadata(
+ const PALMD::Metadata &PALMetadata) {
+ std::string PALMetadataString;
+ auto Error = PALMD::toString(PALMetadata, PALMetadataString);
+ if (Error)
+ return false;
+
+ OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
return true;
}
@@ -239,15 +242,15 @@ bool AMDGPUTargetELFStreamer::EmitHSAMetadata(StringRef YamlString) {
return true;
}
-bool AMDGPUTargetELFStreamer::EmitPalMetadata(ArrayRef<uint32_t> Data) {
+bool AMDGPUTargetELFStreamer::EmitPALMetadata(
+ const PALMD::Metadata &PALMetadata) {
EmitAMDGPUNote(
- MCConstantExpr::create(Data.size() * sizeof(uint32_t), getContext()),
+ MCConstantExpr::create(PALMetadata.size() * sizeof(uint32_t), getContext()),
ElfNote::NT_AMDGPU_PAL_METADATA,
[&](MCELFStreamer &OS){
- for (auto I : Data)
+ for (auto I : PALMetadata)
OS.EmitIntValue(I, sizeof(uint32_t));
}
);
return true;
}
-
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
index a55a6c8c0cb..911b8733a7c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
@@ -54,7 +54,8 @@ public:
/// \returns True on success, false on failure.
virtual bool EmitHSAMetadata(StringRef YamlString) = 0;
- virtual bool EmitPalMetadata(ArrayRef<uint32_t> Data) = 0;
+ /// \returns True on success, false on failure.
+ virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) = 0;
};
class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
@@ -75,7 +76,8 @@ public:
/// \returns True on success, false on failure.
bool EmitHSAMetadata(StringRef YamlString) override;
- bool EmitPalMetadata(ArrayRef<uint32_t> data) override;
+ /// \returns True on success, false on failure.
+ bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
};
class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
@@ -104,7 +106,8 @@ public:
/// \returns True on success, false on failure.
bool EmitHSAMetadata(StringRef YamlString) override;
- bool EmitPalMetadata(ArrayRef<uint32_t> data) override;
+ /// \returns True on success, false on failure.
+ bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
};
}
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