2 files changed, 9 insertions, 9 deletions

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index d9abecd8224..baf27971dd7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1614,7 +1614,7 @@ SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
 
   assert(Op.getValueType() == MVT::f64);
 
-  APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
+  APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
   SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
   SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
 
@@ -1625,7 +1625,7 @@ SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
 
   SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
 
-  APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
+  APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
   SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
 
   EVT SetCCVT =
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 80c815e830b..55eee67a9ee 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -882,11 +882,11 @@ struct OptionalOperand {
 static const fltSemantics *getFltSemantics(unsigned Size) {
   switch (Size) {
   case 4:
-    return &APFloat::IEEEsingle;
+    return &APFloat::IEEEsingle();
   case 8:
-    return &APFloat::IEEEdouble;
+    return &APFloat::IEEEdouble();
   case 2:
-    return &APFloat::IEEEhalf;
+    return &APFloat::IEEEhalf();
   default:
     llvm_unreachable("unsupported fp type");
   }
@@ -935,7 +935,7 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
                                           AsmParser->hasInv2PiInlineImm());
     }
 
-    APFloat FPLiteral(APFloat::IEEEdouble, APInt(64, Imm.Val));
+    APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
     if (!canLosslesslyConvertToFPType(FPLiteral, type))
       return false;
 
@@ -993,7 +993,7 @@ bool AMDGPUOperand::isLiteralImm(MVT type) const {
     return false;
   }
 
-  APFloat FPLiteral(APFloat::IEEEdouble, APInt(64, Imm.Val));
+  APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
   return canLosslesslyConvertToFPType(FPLiteral, type);
 }
 
@@ -1062,7 +1062,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val) const {
     case 4:
     case 2: {
       bool lost;
-      APFloat FPLiteral(APFloat::IEEEdouble, Literal);
+      APFloat FPLiteral(APFloat::IEEEdouble(), Literal);
       // Convert literal to single precision
       FPLiteral.convert(*getFltSemantics(OpSize),
                         APFloat::rmNearestTiesToEven, &lost);
@@ -1130,7 +1130,7 @@ void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const {
   }
 
   bool Lost;
-  APFloat FPLiteral(APFloat::IEEEdouble, Literal);
+  APFloat FPLiteral(APFloat::IEEEdouble(), Literal);
   FPLiteral.convert(*getFltSemantics(Bitwidth / 8),
                     APFloat::rmNearestTiesToEven, &Lost);
   Inst.addOperand(MCOperand::createImm(FPLiteral.bitcastToAPInt().getZExtValue()));