diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SISchedule.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SISchedule.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td index 0f02f5825cb..7af69cb6a46 100644 --- a/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/llvm/lib/Target/AMDGPU/SISchedule.td @@ -46,7 +46,7 @@ def Write64Bit : SchedWrite; // instructions) class SISchedMachineModel : SchedMachineModel { - let CompleteModel = 1; + let CompleteModel = 0; // MicroOpBufferSize = 1 means that instructions will always be added // the ready queue when they become available. This exposes them // to the register pressure analysis. |
