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-rw-r--r--llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp6
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index b8e076f5efd..cc9b46a7558 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -202,12 +202,6 @@ static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) {
MI.setDesc(TII.get(AMDGPU::S_OR_B32));
return true;
}
- case AMDGPU::S_OR_B64_term: {
- // This is only a terminator to get the correct spill code placement during
- // register allocation.
- MI.setDesc(TII.get(AMDGPU::S_OR_B64));
- return true;
- }
case AMDGPU::S_ANDN2_B64_term: {
// This is only a terminator to get the correct spill code placement during
// register allocation.
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