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-rw-r--r--llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 6269dce553f..d042844aa13 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -68,6 +68,14 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
WorkItemIDZ = true;
}
+void SIMachineFunctionInfo::setScratchRSrcReg(const SIRegisterInfo *TRI) {
+ // We need to round up to next multiple of 4.
+ unsigned NextSReg128 = RoundUpToAlignment(NumUserSGPRs + 5, 4);
+ unsigned RegSub0 = AMDGPU::SReg_32RegClass.getRegister(NextSReg128);
+ ScratchRSrcReg = TRI->getMatchingSuperReg(RegSub0, AMDGPU::sub0,
+ &AMDGPU::SReg_128RegClass);
+}
+
SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
MachineFunction *MF,
unsigned FrameIndex,
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