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-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp18
1 files changed, 3 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index bee25c9d184..a14a8929aa4 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3096,12 +3096,13 @@ SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
MachineBasicBlock *RemainderBB;
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
- MachineBasicBlock::iterator Prev = std::prev(MI.getIterator());
+ // Apparently kill flags are only valid if the def is in the same block?
+ if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
+ Src->setIsKill(false);
std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
MachineBasicBlock::iterator I = LoopBB->end();
- MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
@@ -3111,19 +3112,6 @@ SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
.addImm(0)
.addImm(EncodedReg);
- // This is a pain, but we're not allowed to have physical register live-ins
- // yet. Insert a pair of copies if the VGPR0 hack is necessary.
- if (Src && TargetRegisterInfo::isPhysicalRegister(Src->getReg())) {
- unsigned Data0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
- BuildMI(*BB, std::next(Prev), DL, TII->get(AMDGPU::COPY), Data0)
- .add(*Src);
-
- BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::COPY), Src->getReg())
- .addReg(Data0);
-
- MRI.setSimpleHint(Data0, Src->getReg());
- }
-
bundleInstWithWaitcnt(MI);
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
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