diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index ebc686ca83d..4186e221ede 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// // /// \file -/// \brief Custom DAG lowering for SI +/// Custom DAG lowering for SI // //===----------------------------------------------------------------------===// @@ -3785,7 +3785,7 @@ void SITargetLowering::ReplaceNodeResults(SDNode *N, } } -/// \brief Helper function for LowerBRCOND +/// Helper function for LowerBRCOND static SDNode *findUser(SDValue Value, unsigned Opcode) { SDNode *Parent = Value.getNode(); @@ -7129,7 +7129,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); } -/// \brief Helper function for adjustWritemask +/// Helper function for adjustWritemask static unsigned SubIdx2Lane(unsigned Idx) { switch (Idx) { default: return 0; @@ -7140,7 +7140,7 @@ static unsigned SubIdx2Lane(unsigned Idx) { } } -/// \brief Adjust the writemask of MIMG instructions +/// Adjust the writemask of MIMG instructions SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, SelectionDAG &DAG) const { SDNode *Users[4] = { nullptr }; @@ -7262,7 +7262,7 @@ static bool isFrameIndexOp(SDValue Op) { return isa<FrameIndexSDNode>(Op); } -/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG) +/// Legalize target independent instructions (e.g. INSERT_SUBREG) /// with frame index operands. /// LLVM assumes that inputs are to these instructions are registers. SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, @@ -7309,7 +7309,7 @@ SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, return DAG.UpdateNodeOperands(Node, Ops); } -/// \brief Fold the instructions after selecting them. +/// Fold the instructions after selecting them. /// Returns null if users were already updated. SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const { @@ -7383,7 +7383,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, return Node; } -/// \brief Assign the register class depending on the number of +/// Assign the register class depending on the number of /// bits set in the writemask void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const { @@ -7470,7 +7470,7 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG, return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1); } -/// \brief Return a resource descriptor with the 'Add TID' bit enabled +/// Return a resource descriptor with the 'Add TID' bit enabled /// The TID (Thread ID) is multiplied by the stride value (bits [61:48] /// of the resource descriptor) to create an offset, which is added to /// the resource pointer. |
