diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index db725dfc6d0..741cf0ea6cd 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -289,10 +289,6 @@ DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { // as if it has 1 dword, which could be not really so. DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { - if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4) { - return MCDisassembler::Success; - } - int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst); @@ -304,22 +300,25 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); + int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), + AMDGPU::OpName::d16); assert(VDataIdx != -1); assert(DMaskIdx != -1); assert(TFEIdx != -1); bool IsAtomic = (VDstIdx != -1); + bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; if (DMask == 0) return MCDisassembler::Success; - unsigned DstSize = countPopulation(DMask); + unsigned DstSize = IsGather4 ? 4 : countPopulation(DMask); if (DstSize == 1) return MCDisassembler::Success; - bool D16 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::D16; + bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); if (D16 && AMDGPU::hasPackedD16(STI)) { DstSize = (DstSize + 1) / 2; } @@ -335,6 +334,11 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize); } if (NewOpcode == -1) return MCDisassembler::Success; + } else if (IsGather4) { + if (D16 && AMDGPU::hasPackedD16(STI)) + NewOpcode = AMDGPU::getMIMGGatherOpPackedD16(MI.getOpcode()); + else + return MCDisassembler::Success; } else { NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), DstSize); assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); |