diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 99a7d893c93..ede775ffef0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -646,6 +646,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, // Split vector extloads. unsigned MemSize = Query.MMODescrs[0].SizeInBits; + unsigned Align = Query.MMODescrs[0].AlignInBits; + + if (MemSize < DstTy.getSizeInBits()) + MemSize = std::max(MemSize, Align); + if (DstTy.isVector() && DstTy.getSizeInBits() > MemSize) return true; @@ -660,7 +665,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, if (NumRegs == 3 && !ST.hasDwordx3LoadStores()) return true; - unsigned Align = Query.MMODescrs[0].AlignInBits; if (Align < MemSize) { const SITargetLowering *TLI = ST.getTargetLowering(); return !TLI->allowsMisalignedMemoryAccessesImpl(MemSize, AS, Align / 8); @@ -802,14 +806,14 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, unsigned MemSize = Query.MMODescrs[0].SizeInBits; unsigned Align = Query.MMODescrs[0].AlignInBits; - // No extending vector loads. - if (Size > MemSize && Ty0.isVector()) - return false; - // FIXME: Widening store from alignment not valid. if (MemSize < Size) MemSize = std::max(MemSize, Align); + // No extending vector loads. + if (Size > MemSize && Ty0.isVector()) + return false; + switch (MemSize) { case 8: case 16: |
