diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 52ecca76095..bac467928e4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -160,10 +160,31 @@ bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const { bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); DebugLoc DL = I.getDebugLoc(); + unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); + unsigned Opcode; // FIXME: Select store instruction based on address space - MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(AMDGPU::FLAT_STORE_DWORD)) + switch (StoreSize) { + default: + return false; + case 32: + Opcode = AMDGPU::FLAT_STORE_DWORD; + break; + case 64: + Opcode = AMDGPU::FLAT_STORE_DWORDX2; + break; + case 96: + Opcode = AMDGPU::FLAT_STORE_DWORDX3; + break; + case 128: + Opcode = AMDGPU::FLAT_STORE_DWORDX4; + break; + } + + MachineInstr *Flat = BuildMI(*BB, &I, DL, TII.get(Opcode)) .add(I.getOperand(1)) .add(I.getOperand(0)) .addImm(0) // offset |
