diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index f98f57ea047..80a1bc9fe17 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -537,6 +537,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, switch (I.getOpcode()) { default: break; + case TargetOpcode::G_ASHR: case TargetOpcode::G_SITOFP: case TargetOpcode::G_FMUL: case TargetOpcode::G_FADD: @@ -564,6 +565,14 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, return false; } +InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVCSRC(MachineOperand &Root) const { + return {{ + [=](MachineInstrBuilder &MIB) { MIB.add(Root); } + }}; + +} + /// /// This will select either an SGPR or VGPR operand and will save us from /// having to write an extra tablegen pattern. |
