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-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPU.td21
1 files changed, 20 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 0b2badff7cc..46cd112ad49 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -190,6 +190,18 @@ def FeatureScalarStores : SubtargetFeature<"scalar-stores",
"Has store scalar memory instructions"
>;
+def FeatureSDWA : SubtargetFeature<"sdwa",
+ "HasSDWA",
+ "true",
+ "Support SDWA (Sub-DWORD Addressing) extension"
+>;
+
+def FeatureDPP : SubtargetFeature<"dpp",
+ "HasDPP",
+ "true",
+ "Support DPP (Data Parallel Primitives) extension"
+>;
+
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
@@ -337,7 +349,8 @@ def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
- FeatureScalarStores, FeatureInv2PiInlineImm
+ FeatureScalarStores, FeatureInv2PiInlineImm, FeatureSDWA,
+ FeatureDPP
]
>;
@@ -507,6 +520,12 @@ def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">;
+def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
+ AssemblerPredicate<"FeatureSDWA">;
+
+def HasDPP : Predicate<"Subtarget->hasDPP()">,
+ AssemblerPredicate<"FeatureDPP">;
+
class PredicateControl {
Predicate SubtargetPredicate;
Predicate SIAssemblerPredicate = isSICI;
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