diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index d6617617381..cefdf51b50d 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -9348,7 +9348,7 @@ class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode> // ST<OP>{<order>}[<size>] <Ws>, [<Xn|SP>] // ST<OP>{<order>} <Xs>, [<Xn|SP>] -let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in +let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in class BaseCASEncoding<dag oops, dag iops, string asm, string operands, string cstr, list<dag> pattern> : I<oops, iops, asm, operands, cstr, pattern> { @@ -9369,6 +9369,7 @@ class BaseCASEncoding<dag oops, dag iops, string asm, string operands, let Inst{14-10} = 0b11111; let Inst{9-5} = Rn; let Inst{4-0} = Rt; + let Predicates = [HasLSE]; } class BaseCAS<string order, string size, RegisterClass RC> @@ -9401,7 +9402,7 @@ multiclass CompareAndSwapPair<bits<1> Acq, bits<1> Rel, string order> { def d : BaseCASP<order, "", XSeqPairClassOperand>; } -let Predicates = [HasV8_1a] in +let Predicates = [HasLSE] in class BaseSWP<string order, string size, RegisterClass RC> : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "swp" # order # size, "\t$Rs, $Rt, [$Rn]","",[]>, @@ -9424,6 +9425,7 @@ class BaseSWP<string order, string size, RegisterClass RC> let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rt; + let Predicates = [HasLSE]; } multiclass Swap<bits<1> Acq, bits<1> Rel, string order> { @@ -9433,7 +9435,7 @@ multiclass Swap<bits<1> Acq, bits<1> Rel, string order> { let Sz = 0b11, Acq = Acq, Rel = Rel in def d : BaseSWP<order, "", GPR64>; } -let Predicates = [HasV8_1a], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in +let Predicates = [HasLSE], mayLoad = 1, mayStore = 1, hasSideEffects = 1 in class BaseLDOPregister<string op, string order, string size, RegisterClass RC> : I<(outs RC:$Rt),(ins RC:$Rs, GPR64sp:$Rn), "ld" # op # order # size, "\t$Rs, $Rt, [$Rn]","",[]>, @@ -9456,6 +9458,7 @@ class BaseLDOPregister<string op, string order, string size, RegisterClass RC> let Inst{11-10} = 0b00; let Inst{9-5} = Rn; let Inst{4-0} = Rt; + let Predicates = [HasLSE]; } multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel, @@ -9470,7 +9473,7 @@ multiclass LDOPregister<bits<3> opc, string op, bits<1> Acq, bits<1> Rel, def d : BaseLDOPregister<op, order, "", GPR64>; } -let Predicates = [HasV8_1a] in +let Predicates = [HasLSE] in class BaseSTOPregister<string asm, RegisterClass OP, Register Reg, Instruction inst> : InstAlias<asm # "\t$Rs, [$Rn]", (inst Reg, OP:$Rs, GPR64sp:$Rn)>; |
