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-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 41c9a3e78a7..c89becd0c81 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1449,6 +1449,7 @@ static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
bool NeedsNegOutR = RHS->getOpcode() == ISD::OR;
assert((!NeedsNegOutR || !NeedsNegOutL) &&
"Valid conjunction/disjunction tree");
+ (void)NeedsNegOutR;
// Order the side where we need to negate the output flags to RHS so it
// gets emitted first.
if (NeedsNegOutL)
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