1 files changed, 3 insertions, 21 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7cd8ca99e61..4d7f774f84d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2899,27 +2899,9 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
   if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
     return false;
 
-  // Parameters passed in callee saved registers must have the same value in
-  // caller and callee.
-  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
-    const CCValAssign &ArgLoc = ArgLocs[I];
-    if (!ArgLoc.isRegLoc())
-      continue;
-    unsigned Reg = ArgLoc.getLocReg();
-    // Only look at callee saved registers.
-    if (MachineOperand::clobbersPhysReg(CallerPreserved, Reg))
-      continue;
-    // Check that we pass the value used for the caller.
-    // (We look for a CopyFromReg reading a virtual register that is used
-    //  for the function live-in value of register Reg)
-    SDValue Value = OutVals[I];
-    if (Value->getOpcode() != ISD::CopyFromReg)
-      return false;
-    unsigned ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
-    const MachineRegisterInfo &MRI = MF.getRegInfo();
-    if (MRI.getLiveInPhysReg(ArgReg) != Reg)
-      return false;
-  }
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
+    return false;
 
   return true;
 }