diff options
Diffstat (limited to 'llvm/lib/Support/TargetParser.cpp')
| -rw-r--r-- | llvm/lib/Support/TargetParser.cpp | 203 |
1 files changed, 178 insertions, 25 deletions
diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp index 78d0c57a206..e32937e8499 100644 --- a/llvm/lib/Support/TargetParser.cpp +++ b/llvm/lib/Support/TargetParser.cpp @@ -73,8 +73,16 @@ struct { { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 }, { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 }, { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 }, + // Non-standard Arch names. { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE }, - { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE } + { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }, + { "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE }, + { "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE }, + { "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE }, + { "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M }, + { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M }, + { "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 }, + { "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 } }; // List of canonical ARCH names (use getARCHSynonym) // FIXME: TableGen this. @@ -91,6 +99,92 @@ struct { { "sec", ARM::AEK_SEC }, { "virt", ARM::AEK_VIRT } }; +// List of CPU names and their arches. +// The same CPU can have multiple arches and can be default on multiple arches. +// When finding the Arch for a CPU, first-found prevails. Sort them accordingly. +// FIXME: TableGen this. +struct { + const char *Name; + ARM::ArchKind ArchID; + bool Default; +} CPUNames[] = { + { "arm2", ARM::AK_ARMV2, true }, + { "arm6", ARM::AK_ARMV3, true }, + { "arm7m", ARM::AK_ARMV3M, true }, + { "strongarm", ARM::AK_ARMV4, true }, + { "arm7tdmi", ARM::AK_ARMV4T, true }, + { "arm7tdmi-s", ARM::AK_ARMV4T, false }, + { "arm710t", ARM::AK_ARMV4T, false }, + { "arm720t", ARM::AK_ARMV4T, false }, + { "arm9", ARM::AK_ARMV4T, false }, + { "arm9tdmi", ARM::AK_ARMV4T, false }, + { "arm920", ARM::AK_ARMV4T, false }, + { "arm920t", ARM::AK_ARMV4T, false }, + { "arm922t", ARM::AK_ARMV4T, false }, + { "arm9312", ARM::AK_ARMV4T, false }, + { "arm940t", ARM::AK_ARMV4T, false }, + { "ep9312", ARM::AK_ARMV4T, false }, + { "arm10tdmi", ARM::AK_ARMV5, true }, + { "arm10tdmi", ARM::AK_ARMV5T, true }, + { "arm1020t", ARM::AK_ARMV5T, false }, + { "xscale", ARM::AK_XSCALE, true }, + { "xscale", ARM::AK_ARMV5TE, false }, + { "arm9e", ARM::AK_ARMV5TE, false }, + { "arm926ej-s", ARM::AK_ARMV5TE, false }, + { "arm946ej-s", ARM::AK_ARMV5TE, false }, + { "arm966e-s", ARM::AK_ARMV5TE, false }, + { "arm968e-s", ARM::AK_ARMV5TE, false }, + { "arm1020e", ARM::AK_ARMV5TE, false }, + { "arm1022e", ARM::AK_ARMV5TE, true }, + { "iwmmxt", ARM::AK_ARMV5TE, false }, + { "iwmmxt", ARM::AK_IWMMXT, true }, + { "arm1136jf-s", ARM::AK_ARMV6, true }, + { "arm1136j-s", ARM::AK_ARMV6J, true }, + { "arm1136jz-s", ARM::AK_ARMV6J, false }, + { "arm1176j-s", ARM::AK_ARMV6K, false }, + { "mpcore", ARM::AK_ARMV6K, false }, + { "mpcorenovfp", ARM::AK_ARMV6K, false }, + { "arm1176jzf-s", ARM::AK_ARMV6K, true }, + { "arm1176jzf-s", ARM::AK_ARMV6Z, true }, + { "arm1176jzf-s", ARM::AK_ARMV6ZK, true }, + { "arm1156t2-s", ARM::AK_ARMV6T2, true }, + { "arm1156t2f-s", ARM::AK_ARMV6T2, false }, + { "cortex-m0", ARM::AK_ARMV6M, true }, + { "cortex-m0plus", ARM::AK_ARMV6M, false }, + { "cortex-m1", ARM::AK_ARMV6M, false }, + { "sc000", ARM::AK_ARMV6M, false }, + { "cortex-a8", ARM::AK_ARMV7, true }, + { "cortex-a5", ARM::AK_ARMV7A, false }, + { "cortex-a7", ARM::AK_ARMV7A, false }, + { "cortex-a8", ARM::AK_ARMV7A, true }, + { "cortex-a9", ARM::AK_ARMV7A, false }, + { "cortex-a12", ARM::AK_ARMV7A, false }, + { "cortex-a15", ARM::AK_ARMV7A, false }, + { "cortex-a17", ARM::AK_ARMV7A, false }, + { "krait", ARM::AK_ARMV7A, false }, + { "cortex-r4", ARM::AK_ARMV7R, true }, + { "cortex-r4f", ARM::AK_ARMV7R, false }, + { "cortex-r5", ARM::AK_ARMV7R, false }, + { "cortex-r7", ARM::AK_ARMV7R, false }, + { "sc300", ARM::AK_ARMV7M, false }, + { "cortex-m3", ARM::AK_ARMV7M, true }, + { "cortex-m4", ARM::AK_ARMV7M, false }, + { "cortex-m7", ARM::AK_ARMV7M, false }, + { "cortex-a53", ARM::AK_ARMV8A, true }, + { "cortex-a57", ARM::AK_ARMV8A, false }, + { "cortex-a72", ARM::AK_ARMV8A, false }, + { "cyclone", ARM::AK_ARMV8A, false }, + { "generic", ARM::AK_ARMV8_1A, true }, + // Non-standard Arch names. + { "arm1022e", ARM::AK_ARMV5E, true }, + { "arm926ej-s", ARM::AK_ARMV5TEJ, true }, + { "cortex-m0", ARM::AK_ARMV6SM, true }, + { "cortex-a8", ARM::AK_ARMV7L, true }, + { "cortex-m4", ARM::AK_ARMV7EM, true }, + { "swift", ARM::AK_ARMV7S, true }, + // Invalid CPU + { "invalid", ARM::AK_INVALID, true } +}; } // namespace @@ -100,34 +194,47 @@ namespace llvm { // Information by ID // ======================================================= // -const char *ARMTargetParser::getFPUName(unsigned ID) { - if (ID >= ARM::FK_LAST) +const char *ARMTargetParser::getFPUName(unsigned FPUKind) { + if (FPUKind >= ARM::FK_LAST) return nullptr; - return FPUNames[ID].Name; + return FPUNames[FPUKind].Name; } -const char *ARMTargetParser::getArchName(unsigned ID) { - if (ID >= ARM::AK_LAST) +const char *ARMTargetParser::getArchName(unsigned ArchKind) { + if (ArchKind >= ARM::AK_LAST) return nullptr; - return ARCHNames[ID].Name; + return ARCHNames[ArchKind].Name; } -const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) { - if (ID >= ARM::AK_LAST) +const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) { + if (ArchKind >= ARM::AK_LAST) return nullptr; - return ARCHNames[ID].DefaultCPU; + return ARCHNames[ArchKind].DefaultCPU; +} + +unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) { + if (ArchKind >= ARM::AK_LAST) + return ARMBuildAttrs::CPUArch::Pre_v4; + return ARCHNames[ArchKind].DefaultArch; } -unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) { - if (ID >= ARM::AK_LAST) - return 0; - return ARCHNames[ID].DefaultArch; +const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) { + if (ArchExtKind >= ARM::AEK_LAST) + return nullptr; + return ARCHExtNames[ArchExtKind].Name; } -const char *ARMTargetParser::getArchExtName(unsigned ID) { - if (ID >= ARM::AEK_LAST) +const char *ARMTargetParser::getDefaultCPU(StringRef Arch) { + unsigned AK = parseArch(Arch); + if (AK == ARM::AK_INVALID) return nullptr; - return ARCHExtNames[ID].Name; + + // Look for multiple AKs to find the default for pair AK+Name. + for (const auto CPU : CPUNames) { + if (CPU.ArchID == AK && CPU.Default) + return CPU.Name; + } + return nullptr; } // ======================================================= // @@ -154,16 +261,53 @@ StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) { StringRef ARMTargetParser::getArchSynonym(StringRef Arch) { return StringSwitch<StringRef>(Arch) - .Case("armv5tej", "armv5te") - .Case("armv6m", "armv6-m") - .Case("armv7a", "armv7-a") - .Case("armv7r", "armv7-r") - .Case("armv7m", "armv7-m") - .Case("armv8a", "armv8-a") - .Case("armv8.1a", "armv8.1-a") + .Cases("armv6m", "v6m", "armv6-m") + .Cases("armv7a", "v7a", "armv7-a") + .Cases("armv7r", "v7r", "armv7-r") + .Cases("armv7m", "v7m", "armv7-m") + .Cases("armv7em", "v7em", "armv7e-m") + .Cases("armv8", "v8", "armv8-a") + .Cases("armv8a", "v8a", "armv8-a") + .Cases("armv8.1a", "v8.1a", "armv8.1-a") .Default(Arch); } +// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but +// (iwmmxt|xscale)(eb)? is also permitted. If the former, return +// "v.+", if the latter, return unmodified string. If invalid, return "". +StringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) { + size_t offset = StringRef::npos; + StringRef A = Arch; + + // Begins with "arm" / "thumb", move past it. + if (A.startswith("arm")) + offset = 3; + else if (A.startswith("thumb")) + offset = 5; + // Ex. "armebv7", move past the "eb". + if (offset != StringRef::npos && A.substr(offset, 2) == "eb") + offset += 2; + // Or, if it ends with eb ("armv7eb"), chop it off. + else if (A.endswith("eb")) + A = A.substr(0, A.size() - 2); + // Reached the end or a 'v', canonicalise. + if (offset != StringRef::npos && (offset == A.size() || A[offset] == 'v')) + A = A.substr(offset); + + // Empty string mans offset reached the end. Although valid, this arch + // will not have a match in the table. Return the original string. + if (A.empty()) + return Arch; + + // If can't find the arch, return an empty StringRef. + if (parseArch(A) == ARM::AK_INVALID) + A = A.substr(A.size()); + + // Arch will either be a 'v' name (v7a) or a marketing name (xscale) + // or empty, if invalid. + return A; +} + unsigned ARMTargetParser::parseFPU(StringRef FPU) { StringRef Syn = getFPUSynonym(FPU); for (const auto F : FPUNames) { @@ -173,10 +317,11 @@ unsigned ARMTargetParser::parseFPU(StringRef FPU) { return ARM::FK_INVALID; } +// Allows partial match, ex. "v7a" matches "armv7a". unsigned ARMTargetParser::parseArch(StringRef Arch) { StringRef Syn = getArchSynonym(Arch); for (const auto A : ARCHNames) { - if (Syn == A.Name) + if (StringRef(A.Name).endswith(Syn)) return A.ID; } return ARM::AK_INVALID; @@ -190,4 +335,12 @@ unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) { return ARM::AEK_INVALID; } +unsigned ARMTargetParser::parseCPUArch(StringRef CPU) { + for (const auto C : CPUNames) { + if (CPU == C.Name) + return C.ArchID; + } + return ARM::AK_INVALID; +} + } // namespace llvm |
