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-rw-r--r--llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp57
-rw-r--r--llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp2
-rw-r--r--llvm/lib/CodeGen/MachineCombiner.cpp11
-rw-r--r--llvm/lib/CodeGen/TargetSubtargetInfo.cpp70
4 files changed, 16 insertions, 124 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 4c9fe59af42..b8d4466eaba 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -59,7 +59,6 @@
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Comdat.h"
#include "llvm/IR/Constant.h"
@@ -142,10 +141,6 @@ static const char *const CodeViewLineTablesGroupDescription =
STATISTIC(EmittedInsts, "Number of machine instrs printed");
-static cl::opt<bool>
- PrintSchedule("print-schedule", cl::Hidden, cl::init(false),
- cl::desc("Print 'sched: [latency:throughput]' in .s output"));
-
char AsmPrinter::ID = 0;
using gcp_map_type = DenseMap<GCStrategy *, std::unique_ptr<GCMetadataPrinter>>;
@@ -746,10 +741,7 @@ void AsmPrinter::EmitFunctionEntryLabel() {
}
/// emitComments - Pretty-print comments for instructions.
-/// It returns true iff the sched comment was emitted.
-/// Otherwise it returns false.
-static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
- AsmPrinter *AP) {
+static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
const MachineFunction *MF = MI.getMF();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -757,7 +749,6 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
int FI;
const MachineFrameInfo &MFI = MF->getFrameInfo();
- bool Commented = false;
auto getSize =
[&MFI](const SmallVectorImpl<const MachineMemOperand *> &Accesses) {
@@ -777,43 +768,24 @@ static bool emitComments(const MachineInstr &MI, raw_ostream &CommentOS,
if (TII->isLoadFromStackSlotPostFE(MI, FI)) {
if (MFI.isSpillSlotObjectIndex(FI)) {
MMO = *MI.memoperands_begin();
- CommentOS << MMO->getSize() << "-byte Reload";
- Commented = true;
+ CommentOS << MMO->getSize() << "-byte Reload\n";
}
} else if (TII->hasLoadFromStackSlot(MI, Accesses)) {
- if (auto Size = getSize(Accesses)) {
- CommentOS << Size << "-byte Folded Reload";
- Commented = true;
- }
+ if (auto Size = getSize(Accesses))
+ CommentOS << Size << "-byte Folded Reload\n";
} else if (TII->isStoreToStackSlotPostFE(MI, FI)) {
if (MFI.isSpillSlotObjectIndex(FI)) {
MMO = *MI.memoperands_begin();
- CommentOS << MMO->getSize() << "-byte Spill";
- Commented = true;
+ CommentOS << MMO->getSize() << "-byte Spill\n";
}
} else if (TII->hasStoreToStackSlot(MI, Accesses)) {
- if (auto Size = getSize(Accesses)) {
- CommentOS << Size << "-byte Folded Spill";
- Commented = true;
- }
+ if (auto Size = getSize(Accesses))
+ CommentOS << Size << "-byte Folded Spill\n";
}
// Check for spill-induced copies
- if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse)) {
- Commented = true;
- CommentOS << " Reload Reuse";
- }
-
- if (Commented) {
- if (AP->EnablePrintSchedInfo) {
- // If any comment was added above and we need sched info comment then add
- // this new comment just after the above comment w/o "\n" between them.
- CommentOS << " " << MF->getSubtarget().getSchedInfoStr(MI) << "\n";
- return true;
- }
- CommentOS << "\n";
- }
- return false;
+ if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
+ CommentOS << " Reload Reuse\n";
}
/// emitImplicitDef - This method emits the specified machine instruction
@@ -1101,10 +1073,8 @@ void AsmPrinter::EmitFunctionBody() {
}
}
- if (isVerbose() && emitComments(MI, OutStreamer->GetCommentOS(), this)) {
- MachineInstr *MIP = const_cast<MachineInstr *>(&MI);
- MIP->setAsmPrinterFlag(MachineInstr::NoSchedComment);
- }
+ if (isVerbose())
+ emitComments(MI, OutStreamer->GetCommentOS());
switch (MI.getOpcode()) {
case TargetOpcode::CFI_INSTRUCTION:
@@ -1636,11 +1606,6 @@ void AsmPrinter::SetupMachineFunction(MachineFunction &MF) {
}
ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
-
- const TargetSubtargetInfo &STI = MF.getSubtarget();
- EnablePrintSchedInfo = PrintSchedule.getNumOccurrences()
- ? PrintSchedule
- : STI.supportPrintSchedInfo();
}
namespace {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
index 6d5b4be539f..9e6d35c5e9a 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
@@ -154,7 +153,6 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
" we don't have an asm parser for this target\n");
Parser->setAssemblerDialect(Dialect);
Parser->setTargetParser(*TAP.get());
- Parser->setEnablePrintSchedInfo(EnablePrintSchedInfo);
// Enable lexing Masm binary and hex integer literals in intel inline
// assembly.
if (Dialect == InlineAsm::AD_Intel)
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index 1b50b51dc5e..f35f1130817 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -558,16 +558,13 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
continue;
LLVM_DEBUG(if (dump_intrs) {
- dbgs() << "\tFor the Pattern (" << (int)P << ") these instructions could be removed\n";
- for (auto const *InstrPtr : DelInstrs) {
- dbgs() << "\t\t" << STI->getSchedInfoStr(*InstrPtr) << ": ";
+ dbgs() << "\tFor the Pattern (" << (int)P
+ << ") these instructions could be removed\n";
+ for (auto const *InstrPtr : DelInstrs)
InstrPtr->print(dbgs(), false, false, false, TII);
- }
dbgs() << "\tThese instructions could replace the removed ones\n";
- for (auto const *InstrPtr : InsInstrs) {
- dbgs() << "\t\t" << STI->getSchedInfoStr(*InstrPtr) << ": ";
+ for (auto const *InstrPtr : InsInstrs)
InstrPtr->print(dbgs(), false, false, false, TII);
- }
});
bool SubstituteAlways = false;
diff --git a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
index e34f9a1579d..7b29b68597c 100644
--- a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -11,14 +11,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/ADT/Optional.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetSchedule.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/Support/Format.h"
-#include "llvm/Support/raw_ostream.h"
-#include <string>
using namespace llvm;
@@ -66,64 +58,4 @@ bool TargetSubtargetInfo::useAA() const {
return false;
}
-static std::string createSchedInfoStr(unsigned Latency, double RThroughput) {
- static const char *SchedPrefix = " sched: [";
- std::string Comment;
- raw_string_ostream CS(Comment);
- if (RThroughput != 0.0)
- CS << SchedPrefix << Latency << format(":%2.2f", RThroughput)
- << "]";
- else
- CS << SchedPrefix << Latency << ":?]";
- CS.flush();
- return Comment;
-}
-
-/// Returns string representation of scheduler comment
-std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
- if (MI.isPseudo() || MI.isTerminator())
- return std::string();
- // We don't cache TSchedModel because it depends on TargetInstrInfo
- // that could be changed during the compilation
- TargetSchedModel TSchedModel;
- TSchedModel.init(this);
- unsigned Latency = TSchedModel.computeInstrLatency(&MI);
-
- // Add extra latency due to forwarding delays.
- const MCSchedClassDesc &SCDesc = *TSchedModel.resolveSchedClass(&MI);
- Latency +=
- MCSchedModel::getForwardingDelayCycles(getReadAdvanceEntries(SCDesc));
-
- double RThroughput = TSchedModel.computeReciprocalThroughput(&MI);
- return createSchedInfoStr(Latency, RThroughput);
-}
-
-/// Returns string representation of scheduler comment
-std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
- // We don't cache TSchedModel because it depends on TargetInstrInfo
- // that could be changed during the compilation
- TargetSchedModel TSchedModel;
- TSchedModel.init(this);
- unsigned Latency;
- if (TSchedModel.hasInstrSchedModel()) {
- Latency = TSchedModel.computeInstrLatency(MCI);
- // Add extra latency due to forwarding delays.
- const MCSchedModel &SM = *TSchedModel.getMCSchedModel();
- unsigned SClassID = getInstrInfo()->get(MCI.getOpcode()).getSchedClass();
- while (SM.getSchedClassDesc(SClassID)->isVariant())
- SClassID = resolveVariantSchedClass(SClassID, &MCI, SM.ProcID);
- const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SClassID);
- Latency +=
- MCSchedModel::getForwardingDelayCycles(getReadAdvanceEntries(SCDesc));
- } else if (TSchedModel.hasInstrItineraries()) {
- auto *ItinData = TSchedModel.getInstrItineraries();
- Latency = ItinData->getStageLatency(
- getInstrInfo()->get(MCI.getOpcode()).getSchedClass());
- } else
- return std::string();
- double RThroughput = TSchedModel.computeReciprocalThroughput(MCI);
- return createSchedInfoStr(Latency, RThroughput);
-}
-
-void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
-}
+void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
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