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-rw-r--r--llvm/lib/CodeGen/ImplicitNullChecks.cpp6
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp28
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp22
-rw-r--r--llvm/lib/CodeGen/MachineSink.cpp9
4 files changed, 37 insertions, 28 deletions
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index deb49a1ea48..f411ee6745d 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -360,10 +360,10 @@ ImplicitNullChecks::SuitabilityResult
ImplicitNullChecks::isSuitableMemoryOp(MachineInstr &MI, unsigned PointerReg,
ArrayRef<MachineInstr *> PrevInsts) {
int64_t Offset;
- unsigned BaseReg;
+ MachineOperand *BaseOp;
- if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI) ||
- BaseReg != PointerReg)
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) ||
+ !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
return SR_Unsuitable;
// We want the mem access to be issued at a sane offset from PointerReg,
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index bb5fc664c5f..de8c55585d3 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1121,11 +1121,12 @@ void SwingSchedulerDAG::addLoopCarriedDependences(AliasAnalysis *AA) {
// First, perform the cheaper check that compares the base register.
// If they are the same and the load offset is less than the store
// offset, then mark the dependence as loop carried potentially.
- unsigned BaseReg1, BaseReg2;
+ MachineOperand *BaseOp1, *BaseOp2;
int64_t Offset1, Offset2;
- if (TII->getMemOpBaseRegImmOfs(LdMI, BaseReg1, Offset1, TRI) &&
- TII->getMemOpBaseRegImmOfs(MI, BaseReg2, Offset2, TRI)) {
- if (BaseReg1 == BaseReg2 && (int)Offset1 < (int)Offset2) {
+ if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) &&
+ TII->getMemOperandWithOffset(MI, BaseOp2, Offset2, TRI)) {
+ if (BaseOp1->isIdenticalTo(*BaseOp2) &&
+ (int)Offset1 < (int)Offset2) {
assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI, AA) &&
"What happened to the chain edge?");
SDep Dep(Load, SDep::Barrier);
@@ -3246,11 +3247,16 @@ void SwingSchedulerDAG::addBranches(MBBVectorTy &PrologBBs,
/// during each iteration. Set Delta to the amount of the change.
bool SwingSchedulerDAG::computeDelta(MachineInstr &MI, unsigned &Delta) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- unsigned BaseReg;
+ MachineOperand *BaseOp;
int64_t Offset;
- if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
return false;
+ if (!BaseOp->isReg())
+ return false;
+
+ unsigned BaseReg = BaseOp->getReg();
+
MachineRegisterInfo &MRI = MF.getRegInfo();
// Check if there is a Phi. If so, get the definition in the loop.
MachineInstr *BaseDef = MRI.getVRegDef(BaseReg);
@@ -3653,19 +3659,19 @@ bool SwingSchedulerDAG::isLoopCarriedDep(SUnit *Source, const SDep &Dep,
if (!computeDelta(*SI, DeltaS) || !computeDelta(*DI, DeltaD))
return true;
- unsigned BaseRegS, BaseRegD;
+ MachineOperand *BaseOpS, *BaseOpD;
int64_t OffsetS, OffsetD;
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- if (!TII->getMemOpBaseRegImmOfs(*SI, BaseRegS, OffsetS, TRI) ||
- !TII->getMemOpBaseRegImmOfs(*DI, BaseRegD, OffsetD, TRI))
+ if (!TII->getMemOperandWithOffset(*SI, BaseOpS, OffsetS, TRI) ||
+ !TII->getMemOperandWithOffset(*DI, BaseOpD, OffsetD, TRI))
return true;
- if (BaseRegS != BaseRegD)
+ if (!BaseOpS->isIdenticalTo(*BaseOpD))
return true;
// Check that the base register is incremented by a constant value for each
// iteration.
- MachineInstr *Def = MRI.getVRegDef(BaseRegS);
+ MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
if (!Def || !Def->isPHI())
return true;
unsigned InitVal = 0;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3b163fa6340..e423c89b1db 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1483,15 +1483,15 @@ namespace {
class BaseMemOpClusterMutation : public ScheduleDAGMutation {
struct MemOpInfo {
SUnit *SU;
- unsigned BaseReg;
+ MachineOperand *BaseOp;
int64_t Offset;
- MemOpInfo(SUnit *su, unsigned reg, int64_t ofs)
- : SU(su), BaseReg(reg), Offset(ofs) {}
+ MemOpInfo(SUnit *su, MachineOperand *Op, int64_t ofs)
+ : SU(su), BaseOp(Op), Offset(ofs) {}
- bool operator<(const MemOpInfo&RHS) const {
- return std::tie(BaseReg, Offset, SU->NodeNum) <
- std::tie(RHS.BaseReg, RHS.Offset, RHS.SU->NodeNum);
+ bool operator<(const MemOpInfo &RHS) const {
+ return std::make_tuple(BaseOp->getReg(), Offset, SU->NodeNum) <
+ std::make_tuple(RHS.BaseOp->getReg(), RHS.Offset, RHS.SU->NodeNum);
}
};
@@ -1547,10 +1547,10 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) {
SmallVector<MemOpInfo, 32> MemOpRecords;
for (SUnit *SU : MemOps) {
- unsigned BaseReg;
+ MachineOperand *BaseOp;
int64_t Offset;
- if (TII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseReg, Offset, TRI))
- MemOpRecords.push_back(MemOpInfo(SU, BaseReg, Offset));
+ if (TII->getMemOperandWithOffset(*SU->getInstr(), BaseOp, Offset, TRI))
+ MemOpRecords.push_back(MemOpInfo(SU, BaseOp, Offset));
}
if (MemOpRecords.size() < 2)
return;
@@ -1560,8 +1560,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {
SUnit *SUa = MemOpRecords[Idx].SU;
SUnit *SUb = MemOpRecords[Idx+1].SU;
- if (TII->shouldClusterMemOps(*SUa->getInstr(), MemOpRecords[Idx].BaseReg,
- *SUb->getInstr(), MemOpRecords[Idx+1].BaseReg,
+ if (TII->shouldClusterMemOps(*MemOpRecords[Idx].BaseOp,
+ *MemOpRecords[Idx + 1].BaseOp,
ClusterLength) &&
DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index d45855407f2..cdc597db640 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -716,9 +716,12 @@ static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
!PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit))
return false;
- unsigned BaseReg;
+ MachineOperand *BaseOp;
int64_t Offset;
- if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
+ if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
+ return false;
+
+ if (!BaseOp->isReg())
return false;
if (!(MI.mayLoad() && !MI.isPredicable()))
@@ -731,7 +734,7 @@ static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
(MBP.Predicate == MachineBranchPredicate::PRED_NE ||
MBP.Predicate == MachineBranchPredicate::PRED_EQ) &&
- MBP.LHS.getReg() == BaseReg;
+ MBP.LHS.getReg() == BaseOp->getReg();
}
/// Sink an instruction and its associated debug instructions. If the debug
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