diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 35 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 |
2 files changed, 36 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index ead239f604d..3cdf8d2941d 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1201,7 +1201,10 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx, unsigned Flag = getOperand(FlagIdx).getImm(); unsigned RCID; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) + if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse || + InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef || + InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && + InlineAsm::hasRegClassConstraint(Flag, RCID)) return TRI->getRegClass(RCID); // Assume that all registers in a memory operand are pointers. @@ -1826,13 +1829,41 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, } unsigned RCID = 0; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { + if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && + InlineAsm::hasRegClassConstraint(Flag, RCID)) { if (TRI) { OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); } else OS << ":RC" << RCID; } + if (InlineAsm::isMemKind(Flag)) { + unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); + switch (MCID) { + case InlineAsm::Constraint_es: OS << ":es"; break; + case InlineAsm::Constraint_i: OS << ":i"; break; + case InlineAsm::Constraint_m: OS << ":m"; break; + case InlineAsm::Constraint_o: OS << ":o"; break; + case InlineAsm::Constraint_v: OS << ":v"; break; + case InlineAsm::Constraint_Q: OS << ":Q"; break; + case InlineAsm::Constraint_R: OS << ":R"; break; + case InlineAsm::Constraint_S: OS << ":S"; break; + case InlineAsm::Constraint_T: OS << ":T"; break; + case InlineAsm::Constraint_Um: OS << ":Um"; break; + case InlineAsm::Constraint_Un: OS << ":Un"; break; + case InlineAsm::Constraint_Uq: OS << ":Uq"; break; + case InlineAsm::Constraint_Us: OS << ":Us"; break; + case InlineAsm::Constraint_Ut: OS << ":Ut"; break; + case InlineAsm::Constraint_Uv: OS << ":Uv"; break; + case InlineAsm::Constraint_Uy: OS << ":Uy"; break; + case InlineAsm::Constraint_X: OS << ":X"; break; + case InlineAsm::Constraint_Z: OS << ":Z"; break; + case InlineAsm::Constraint_ZC: OS << ":ZC"; break; + case InlineAsm::Constraint_Zy: OS << ":Zy"; break; + default: OS << ":?"; break; + } + } + unsigned TiedTo = 0; if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) OS << " tiedto:$" << TiedTo; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index a46d9aaa9d7..1d61657194c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1950,15 +1950,15 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, // Otherwise, this is a memory operand. Ask the target to select it. std::vector<SDValue> SelOps; - if (SelectInlineAsmMemoryOperand(InOps[i+1], - InlineAsm::getMemoryConstraintID(Flags), - SelOps)) + unsigned ConstraintID = InlineAsm::getMemoryConstraintID(Flags); + if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps)) report_fatal_error("Could not match memory address. Inline asm" " failure!"); // Add this to the output node. unsigned NewFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); + NewFlags = InlineAsm::getFlagWordForMem(NewFlags, ConstraintID); Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32)); Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); i += 2; |
