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-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp27
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIRParser.cpp4
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp42
-rw-r--r--llvm/lib/CodeGen/MachineRegisterInfo.cpp2
4 files changed, 56 insertions, 19 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 696ba48e97c..2147651c4ef 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -877,7 +877,7 @@ bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
bool MIParser::parseRegisterTiedDefIndex(unsigned &TiedDefIdx) {
if (!consumeIfPresent(MIToken::kw_tied_def))
- return error("expected 'tied-def' after '('");
+ return true;
if (Token.isNot(MIToken::IntegerLiteral))
return error("expected an integer literal after 'tied-def'");
if (getUnsigned(TiedDefIdx))
@@ -957,16 +957,28 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
if (!TargetRegisterInfo::isVirtualRegister(Reg))
return error("subregister index expects a virtual register");
}
+ MachineRegisterInfo &MRI = MF.getRegInfo();
if ((Flags & RegState::Define) == 0) {
if (consumeIfPresent(MIToken::lparen)) {
unsigned Idx;
- if (parseRegisterTiedDefIndex(Idx))
- return true;
- TiedDefIdx = Idx;
+ if (!parseRegisterTiedDefIndex(Idx))
+ TiedDefIdx = Idx;
+ else {
+ // Try a redundant low-level type.
+ LLT Ty;
+ if (parseLowLevelType(Token.location(), Ty))
+ return error("expected tied-def or low-level type after '('");
+
+ if (expectAndConsume(MIToken::rparen))
+ return true;
+
+ if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
+ return error("inconsistent type for generic virtual register");
+
+ MRI.setType(Reg, Ty);
+ }
}
} else if (consumeIfPresent(MIToken::lparen)) {
- MachineRegisterInfo &MRI = MF.getRegInfo();
-
// Virtual registers may have a size with GlobalISel.
if (!TargetRegisterInfo::isVirtualRegister(Reg))
return error("unexpected size on physical register");
@@ -980,6 +992,9 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
if (expectAndConsume(MIToken::rparen))
return true;
+ if (MRI.getType(Reg).isValid() && MRI.getType(Reg) != Ty)
+ return error("inconsistent type for generic virtual register");
+
MRI.setType(Reg, Ty);
} else if (PFS.GenericVRegs.count(Reg)) {
// Generic virtual registers must have a size.
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index e7fdcc0afd8..104d7d18812 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -415,7 +415,7 @@ bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,
if (StringRef(VReg.Class.Value).equals("_")) {
// This is a generic virtual register.
// The size will be set appropriately when we reach the definition.
- Reg = RegInfo.createGenericVirtualRegister(LLT::scalar(1));
+ Reg = RegInfo.createGenericVirtualRegister(LLT{});
PFS.GenericVRegs.insert(Reg);
} else {
const auto *RC = getRegClass(MF, VReg.Class.Value);
@@ -428,7 +428,7 @@ bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,
VReg.Class.SourceRange.Start,
Twine("use of undefined register class or register bank '") +
VReg.Class.Value + "'");
- Reg = RegInfo.createGenericVirtualRegister(LLT::scalar(1));
+ Reg = RegInfo.createGenericVirtualRegister(LLT{});
RegInfo.setRegBank(Reg, *RegBank);
PFS.GenericVRegs.insert(Reg);
}
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index e293a0743eb..11d84d7c350 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -14,6 +14,7 @@
#include "MIRPrinter.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallBitVector.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineConstantPool.h"
@@ -123,7 +124,7 @@ public:
void printTargetFlags(const MachineOperand &Op);
void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
unsigned I, bool ShouldPrintRegisterTies,
- const MachineRegisterInfo *MRI = nullptr, bool IsDef = false);
+ LLT TypeToPrint, bool IsDef = false);
void print(const MachineMemOperand &Op);
void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
@@ -223,7 +224,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
else {
VReg.Class = std::string("_");
- assert(RegInfo.getType(Reg).isValid() &&
+ assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
"Generic registers must have a valid type");
}
unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
@@ -542,6 +543,27 @@ static bool hasComplexRegisterTies(const MachineInstr &MI) {
return false;
}
+static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
+ SmallBitVector &PrintedTypes,
+ const MachineRegisterInfo &MRI) {
+ const MachineOperand &Op = MI.getOperand(OpIdx);
+ if (!Op.isReg())
+ return LLT{};
+
+ if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
+ return MRI.getType(Op.getReg());
+
+ auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
+ if (!OpInfo.isGenericType())
+ return MRI.getType(Op.getReg());
+
+ if (PrintedTypes[OpInfo.getGenericTypeIndex()])
+ return LLT{};
+
+ PrintedTypes.set(OpInfo.getGenericTypeIndex());
+ return MRI.getType(Op.getReg());
+}
+
void MIPrinter::print(const MachineInstr &MI) {
const auto *MF = MI.getParent()->getParent();
const auto &MRI = MF->getRegInfo();
@@ -553,6 +575,7 @@ void MIPrinter::print(const MachineInstr &MI) {
if (MI.isCFIInstruction())
assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
+ SmallBitVector PrintedTypes(8);
bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
unsigned I = 0, E = MI.getNumOperands();
for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
@@ -560,7 +583,8 @@ void MIPrinter::print(const MachineInstr &MI) {
++I) {
if (I)
OS << ", ";
- print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, &MRI,
+ print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
+ getTypeToPrint(MI, I, PrintedTypes, MRI),
/*IsDef=*/true);
}
@@ -576,7 +600,8 @@ void MIPrinter::print(const MachineInstr &MI) {
for (; I < E; ++I) {
if (NeedComma)
OS << ", ";
- print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);
+ print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
+ getTypeToPrint(MI, I, PrintedTypes, MRI));
NeedComma = true;
}
@@ -748,8 +773,8 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
}
void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
- unsigned I, bool ShouldPrintRegisterTies,
- const MachineRegisterInfo *MRI, bool IsDef) {
+ unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
+ bool IsDef) {
printTargetFlags(Op);
switch (Op.getType()) {
case MachineOperand::MO_Register:
@@ -776,9 +801,8 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
- assert((!IsDef || MRI) && "for IsDef, MRI must be provided");
- if (IsDef && MRI->getType(Op.getReg()).isValid())
- OS << '(' << MRI->getType(Op.getReg()) << ')';
+ if (TypeToPrint.isValid())
+ OS << '(' << TypeToPrint << ')';
break;
case MachineOperand::MO_Immediate:
OS << Op.getImm();
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index a16211cfa2b..ca89a1ff7bc 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -126,8 +126,6 @@ void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
unsigned
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty) {
- assert(Ty.isValid() && "Cannot create empty virtual register");
-
// New virtual register number.
unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
VRegInfo.grow(Reg);
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