diff options
Diffstat (limited to 'llvm/lib/CodeGen')
6 files changed, 1 insertions, 56 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index ea537fff168..2cfcf77b17a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -147,10 +147,6 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo); break; - case ISD::UABSDIFF: - case ISD::SABSDIFF: - Res = PromoteIntRes_SimpleIntBinOp(N); - break; } // If the result is null then the sub-method took care of registering it. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 8295b2a19dd..eddf666c9c3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -105,7 +105,6 @@ class VectorLegalizer { SDValue ExpandLoad(SDValue Op); SDValue ExpandStore(SDValue Op); SDValue ExpandFNEG(SDValue Op); - SDValue ExpandABSDIFF(SDValue Op); /// \brief Implements vector promotion. /// @@ -330,8 +329,6 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::SMAX: case ISD::UMIN: case ISD::UMAX: - case ISD::UABSDIFF: - case ISD::SABSDIFF: QueryType = Node->getValueType(0); break; case ISD::FP_ROUND_INREG: @@ -718,42 +715,11 @@ SDValue VectorLegalizer::Expand(SDValue Op) { return ExpandFNEG(Op); case ISD::SETCC: return UnrollVSETCC(Op); - case ISD::UABSDIFF: - case ISD::SABSDIFF: - return ExpandABSDIFF(Op); default: return DAG.UnrollVectorOp(Op.getNode()); } } -SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) { - SDLoc dl(Op); - SDValue Op0 = Op.getOperand(0); - SDValue Op1 = Op.getOperand(1); - EVT VT = Op.getValueType(); - - // For unsigned intrinsic, promote the type to handle unsigned overflow. - bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF); - if (isUabsdiff) { - VT = VT.widenIntegerVectorElementType(*DAG.getContext()); - Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0); - Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1); - } - - SDNodeFlags Flags; - Flags.setNoSignedWrap(!isUabsdiff); - SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags); - if (isUabsdiff) - return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub); - - SDValue Cmp = - DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(), - *DAG.getContext(), VT), - Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE)); - SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags); - return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg); -} - SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { // Lower a select instruction where the condition is a scalar and the // operands are vectors. Lower this select to VSELECT and implement it diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 96b8cc065f5..d9f02f4ae72 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -684,8 +684,6 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { case ISD::SMAX: case ISD::UMIN: case ISD::UMAX: - case ISD::UABSDIFF: - case ISD::SABSDIFF: SplitVecRes_BinOp(N, Lo, Hi); break; case ISD::FMA: diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 867b9562019..91aa3eee01b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -4880,18 +4880,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { getValue(I.getArgOperand(0)).getValueType(), getValue(I.getArgOperand(0)))); return nullptr; - case Intrinsic::uabsdiff: - setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl, - getValue(I.getArgOperand(0)).getValueType(), - getValue(I.getArgOperand(0)), - getValue(I.getArgOperand(1)))); - return nullptr; - case Intrinsic::sabsdiff: - setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl, - getValue(I.getArgOperand(0)).getValueType(), - getValue(I.getArgOperand(0)), - getValue(I.getArgOperand(1)))); - return nullptr; case Intrinsic::cttz: { SDValue Arg = getValue(I.getArgOperand(0)); ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 7c5492b554c..a1c6c4c1dd6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -235,8 +235,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SHL_PARTS: return "shl_parts"; case ISD::SRA_PARTS: return "sra_parts"; case ISD::SRL_PARTS: return "srl_parts"; - case ISD::UABSDIFF: return "uabsdiff"; - case ISD::SABSDIFF: return "sabsdiff"; // Conversion operators. case ISD::SIGN_EXTEND: return "sign_extend"; diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 68bca2e7036..c5972263046 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -826,8 +826,7 @@ void TargetLoweringBase::initActions() { setOperationAction(ISD::USUBO, VT, Expand); setOperationAction(ISD::SMULO, VT, Expand); setOperationAction(ISD::UMULO, VT, Expand); - setOperationAction(ISD::UABSDIFF, VT, Expand); - setOperationAction(ISD::SABSDIFF, VT, Expand); + setOperationAction(ISD::BITREVERSE, VT, Expand); // These library functions default to expand. |
