diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 | 
2 files changed, 0 insertions, 20 deletions
| diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 8d1ea8d3a43..a2c5396bb93 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1589,23 +1589,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {        AddLegalizedOperand(SDValue(Node, i), Tmp1);      }      return Tmp2; -   case ISD::EXTRACT_SUBREG: { -      Tmp1 = LegalizeOp(Node->getOperand(0)); -      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); -      assert(idx && "Operand must be a constant"); -      Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); -      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); -    } -    break; -  case ISD::INSERT_SUBREG: { -      Tmp1 = LegalizeOp(Node->getOperand(0)); -      Tmp2 = LegalizeOp(Node->getOperand(1)); -      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); -      assert(idx && "Operand must be a constant"); -      Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); -      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); -    } -    break;    case ISD::BUILD_VECTOR:      switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {      default: assert(0 && "This action is not supported yet!"); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 448d7608681..3ff0352f668 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5165,9 +5165,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {    case ISD::SRA_PARTS:   return "sra_parts";    case ISD::SRL_PARTS:   return "srl_parts"; -  case ISD::EXTRACT_SUBREG:     return "extract_subreg"; -  case ISD::INSERT_SUBREG:      return "insert_subreg"; -    // Conversion operators.    case ISD::SIGN_EXTEND: return "sign_extend";    case ISD::ZERO_EXTEND: return "zero_extend"; | 

