diff options
Diffstat (limited to 'llvm/lib/CodeGen')
38 files changed, 151 insertions, 151 deletions
diff --git a/llvm/lib/CodeGen/AllocationOrder.cpp b/llvm/lib/CodeGen/AllocationOrder.cpp index 3d106945e19..8e8c1d8e08d 100644 --- a/llvm/lib/CodeGen/AllocationOrder.cpp +++ b/llvm/lib/CodeGen/AllocationOrder.cpp @@ -43,7 +43,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, if (!Hints.empty()) { dbgs() << "hints:"; for (unsigned I = 0, E = Hints.size(); I != E; ++I) - dbgs() << ' ' << PrintReg(Hints[I], TRI); + dbgs() << ' ' << printReg(Hints[I], TRI); dbgs() << '\n'; } }); diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index f155ce33e2f..c9b0f9aa556 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -802,7 +802,7 @@ void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const { SmallString<128> Str; raw_svector_ostream OS(Str); OS << "implicit-def: " - << PrintReg(RegNo, MF->getSubtarget().getRegisterInfo()); + << printReg(RegNo, MF->getSubtarget().getRegisterInfo()); OutStreamer->AddComment(OS.str()); OutStreamer->AddBlankLine(); @@ -816,7 +816,7 @@ static void emitKill(const MachineInstr *MI, AsmPrinter &AP) { const MachineOperand &Op = MI->getOperand(i); assert(Op.isReg() && "KILL instruction must have only register operands"); OS << ' ' - << PrintReg(Op.getReg(), + << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo()) << (Op.isDef() ? "<def>" : "<kill>"); } @@ -903,7 +903,7 @@ static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) { } if (MemLoc) OS << '['; - OS << PrintReg(Reg, AP.MF->getSubtarget().getRegisterInfo()); + OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo()); } if (MemLoc) diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index 892b8769f3c..ef4e2aaaf48 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -526,7 +526,7 @@ bool DetectDeadLanes::runOnce(MachineFunction &MF) { for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); const VRegInfo &Info = VRegInfos[RegIdx]; - dbgs() << PrintReg(Reg, nullptr) + dbgs() << printReg(Reg, nullptr) << " Used: " << PrintLaneMask(Info.UsedLanes) << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n'; } diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp index b3dea5ee008..bb181b7e165 100644 --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -317,7 +317,7 @@ bool SSAIfConv::findInsertionPoint() { dbgs() << "Would clobber"; for (SparseSet<unsigned>::const_iterator i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i) - dbgs() << ' ' << PrintRegUnit(*i, TRI); + dbgs() << ' ' << printRegUnit(*i, TRI); dbgs() << " live before " << *I; }); continue; diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp index 8cc44c505cb..8e16470b6f9 100644 --- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp @@ -113,7 +113,7 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) { MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first; DEBUG(dbgs() << "Inserted: " << *LocalizedMI); } - DEBUG(dbgs() << "Update use with: " << PrintReg(NewVRegIt->second) + DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second) << '\n'); // Update the user reg. MOUse.setReg(NewVRegIt->second); diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index 8c40608c8f1..36ce1c220cb 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -159,7 +159,7 @@ bool RegBankSelect::repairReg( // same types because the type is a placeholder when this function is called. MachineInstr *MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); - DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst) + DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst) << '\n'); // TODO: // Check if MI is legal. if not, we need to legalize all the diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index a474601d5f3..27039493413 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -432,9 +432,9 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) { } unsigned OrigReg = MO.getReg(); unsigned NewReg = *NewRegs.begin(); - DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr)); + DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); MO.setReg(NewReg); - DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr)); + DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); // The OperandsMapper creates plain scalar, we may have to fix that. // Check if the types match and if not, fix that. @@ -753,13 +753,13 @@ void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS, if (!IsFirst) OS << ", "; IsFirst = false; - OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; + OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; bool IsFirstNewVReg = true; for (unsigned VReg : getVRegs(Idx)) { if (!IsFirstNewVReg) OS << ", "; IsFirstNewVReg = false; - OS << PrintReg(VReg, TRI); + OS << printReg(VReg, TRI); } OS << "])"; } diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index cf4099773a1..aff6189283e 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -921,7 +921,7 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill, /// spillAroundUses - insert spill code around each use of Reg. void InlineSpiller::spillAroundUses(unsigned Reg) { - DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); + DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n'); LiveInterval &OldLI = LIS.getInterval(Reg); // Iterate over instructions using Reg. @@ -1077,7 +1077,7 @@ void InlineSpiller::spill(LiveRangeEdit &edit) { DEBUG(dbgs() << "Inline spilling " << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) << ':' << edit.getParent() - << "\nFrom original " << PrintReg(Original) << '\n'); + << "\nFrom original " << printReg(Original) << '\n'); assert(edit.getParent().isSpillable() && "Attempting to spill already spilled value."); assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index 777c6ec4458..3d4e35e5bdc 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -457,7 +457,7 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI, // Check if the register is the location of a debug value. for (unsigned ID : OpenRanges.getVarLocs()) { if (VarLocIDs[ID].isDescribedByReg() == Reg) { - DEBUG(dbgs() << "Spilling Register " << PrintReg(Reg, TRI) << '(' + DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar()->getName() << ")\n"); // Create a DBG_VALUE instruction to describe the Var in its spilled diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp index c320b62315e..b306932832c 100644 --- a/llvm/lib/CodeGen/LiveInterval.cpp +++ b/llvm/lib/CodeGen/LiveInterval.cpp @@ -986,7 +986,7 @@ void LiveInterval::SubRange::print(raw_ostream &OS) const { } void LiveInterval::print(raw_ostream &OS) const { - OS << PrintReg(reg) << ' '; + OS << printReg(reg) << ' '; super::print(OS); // Print subranges for (const SubRange &SR : subranges()) diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp index 819b5230db4..b26628b3b5f 100644 --- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -157,7 +157,7 @@ void LiveIntervals::print(raw_ostream &OS, const Module* ) const { // Dump the regunits. for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit) if (LiveRange *LR = RegUnitRanges[Unit]) - OS << PrintRegUnit(Unit, TRI) << ' ' << *LR << '\n'; + OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; // Dump the virtregs. for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { @@ -335,7 +335,7 @@ void LiveIntervals::computeLiveInRegUnits() { } VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator()); (void)VNI; - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id); } } DEBUG(dbgs() << '\n'); @@ -995,11 +995,11 @@ private: DEBUG({ dbgs() << " "; if (TargetRegisterInfo::isVirtualRegister(Reg)) { - dbgs() << PrintReg(Reg); + dbgs() << printReg(Reg); if (LaneMask.any()) dbgs() << " L" << PrintLaneMask(LaneMask); } else { - dbgs() << PrintRegUnit(Reg, &TRI); + dbgs() << printRegUnit(Reg, &TRI); } dbgs() << ":\t" << LR << '\n'; }); diff --git a/llvm/lib/CodeGen/LiveIntervalUnion.cpp b/llvm/lib/CodeGen/LiveIntervalUnion.cpp index 7ab69658b32..3e742a6c2f2 100644 --- a/llvm/lib/CodeGen/LiveIntervalUnion.cpp +++ b/llvm/lib/CodeGen/LiveIntervalUnion.cpp @@ -87,7 +87,7 @@ LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const { } for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { OS << " [" << SI.start() << ' ' << SI.stop() << "):" - << PrintReg(SI.value()->reg, TRI); + << printReg(SI.value()->reg, TRI); } OS << '\n'; } diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp index 779f601e402..f4b43a9b8ea 100644 --- a/llvm/lib/CodeGen/LivePhysRegs.cpp +++ b/llvm/lib/CodeGen/LivePhysRegs.cpp @@ -126,7 +126,7 @@ void LivePhysRegs::print(raw_ostream &OS) const { } for (const_iterator I = begin(), E = end(); I != E; ++I) - OS << " " << PrintReg(*I, TRI); + OS << " " << printReg(*I, TRI); OS << "\n"; } diff --git a/llvm/lib/CodeGen/LiveRangeCalc.cpp b/llvm/lib/CodeGen/LiveRangeCalc.cpp index 2b8993d31d9..0074a9fd907 100644 --- a/llvm/lib/CodeGen/LiveRangeCalc.cpp +++ b/llvm/lib/CodeGen/LiveRangeCalc.cpp @@ -364,7 +364,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, #ifndef NDEBUG if (MBB->pred_empty()) { MBB->getParent()->verify(); - errs() << "Use of " << PrintReg(PhysReg) + errs() << "Use of " << printReg(PhysReg) << " does not have a corresponding definition on every path:\n"; const MachineInstr *MI = Indexes->getInstructionFromIndex(Use); if (MI != nullptr) @@ -376,7 +376,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, !MBB->isLiveIn(PhysReg)) { MBB->getParent()->verify(); const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); - errs() << "The register " << PrintReg(PhysReg, TRI) + errs() << "The register " << printReg(PhysReg, TRI) << " needs to be live in to BB#" << MBB->getNumber() << ", but is missing from the live-in list.\n"; report_fatal_error("Invalid global physical register"); diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp index 61fbfdd64a2..31be5e23344 100644 --- a/llvm/lib/CodeGen/LiveRangeEdit.cpp +++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp @@ -465,7 +465,7 @@ LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF, if (MRI.recomputeRegClass(LI.reg)) DEBUG({ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); - dbgs() << "Inflated " << PrintReg(LI.reg) << " to " + dbgs() << "Inflated " << printReg(LI.reg) << " to " << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n'; }); VRAI.calculateSpillWeightAndHint(LI); diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index fe1972a3c9e..92e7cf8a9c8 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -102,14 +102,14 @@ static bool foreachUnit(const TargetRegisterInfo *TRI, } void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { - DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) - << " to " << PrintReg(PhysReg, TRI) << ':'); + DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) + << " to " << printReg(PhysReg, TRI) << ':'); assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); VRM->assignVirt2Phys(VirtReg.reg, PhysReg); foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); Matrix[Unit].unify(VirtReg, Range); return false; }); @@ -120,13 +120,13 @@ void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { void LiveRegMatrix::unassign(LiveInterval &VirtReg) { unsigned PhysReg = VRM->getPhys(VirtReg.reg); - DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) - << " from " << PrintReg(PhysReg, TRI) << ':'); + DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) + << " from " << printReg(PhysReg, TRI) << ':'); VRM->clearVirt(VirtReg.reg); foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { - DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI)); + DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI)); Matrix[Unit].extract(VirtReg, Range); return false; }); diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 8dd67c66e62..02b0b7ea5e5 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -192,8 +192,8 @@ template <> struct BlockScalarTraits<Module> { } // end namespace yaml } // end namespace llvm -static void printReg(unsigned Reg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { +static void printRegMIR(unsigned Reg, raw_ostream &OS, + const TargetRegisterInfo *TRI) { // TODO: Print Stack Slots. if (!Reg) OS << '_'; @@ -205,10 +205,10 @@ static void printReg(unsigned Reg, raw_ostream &OS, llvm_unreachable("Can't print this kind of register yet"); } -static void printReg(unsigned Reg, yaml::StringValue &Dest, - const TargetRegisterInfo *TRI) { +static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, + const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); } void MIRPrinter::print(const MachineFunction &MF) { @@ -262,7 +262,7 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, if (RegMask[I / 32] & (1u << (I % 32))) { if (IsRegInRegMaskFound) OS << ','; - printReg(I, OS, TRI); + printRegMIR(I, OS, TRI); IsRegInRegMaskFound = true; } } @@ -305,16 +305,16 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI); unsigned PreferredReg = RegInfo.getSimpleHint(Reg); if (PreferredReg) - printReg(PreferredReg, VReg.PreferredRegister, TRI); + printRegMIR(PreferredReg, VReg.PreferredRegister, TRI); MF.VirtualRegisters.push_back(VReg); } // Print the live ins. for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) { yaml::MachineFunctionLiveIn LiveIn; - printReg(LI.first, LiveIn.Register, TRI); + printRegMIR(LI.first, LiveIn.Register, TRI); if (LI.second) - printReg(LI.second, LiveIn.VirtualRegister, TRI); + printRegMIR(LI.second, LiveIn.VirtualRegister, TRI); MF.LiveIns.push_back(LiveIn); } @@ -324,7 +324,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, std::vector<yaml::FlowStringValue> CalleeSavedRegisters; for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) { yaml::FlowStringValue Reg; - printReg(*I, Reg, TRI); + printRegMIR(*I, Reg, TRI); CalleeSavedRegisters.push_back(Reg); } MF.CalleeSavedRegisters = CalleeSavedRegisters; @@ -415,7 +415,7 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF, for (const auto &CSInfo : MFI.getCalleeSavedInfo()) { yaml::StringValue Reg; - printReg(CSInfo.getReg(), Reg, TRI); + printRegMIR(CSInfo.getReg(), Reg, TRI); auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx()); assert(StackObjectInfo != StackObjectOperandMapping.end() && "Invalid stack object index"); @@ -648,7 +648,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { if (!First) OS << ", "; First = false; - printReg(LI.PhysReg, OS, &TRI); + printRegMIR(LI.PhysReg, OS, &TRI); if (!LI.LaneMask.all()) OS << ":0x" << PrintLaneMask(LI.LaneMask); } @@ -949,7 +949,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, OS << "early-clobber "; if (Op.isDebug()) OS << "debug-use "; - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); // Print the sub register. if (Op.getSubReg() != 0) OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); @@ -1041,7 +1041,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (IsCommaNeeded) OS << ", "; - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); IsCommaNeeded = true; } } @@ -1210,7 +1210,7 @@ static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, OS << "<badreg>"; return; } - printReg(Reg, OS, TRI); + printRegMIR(Reg, OS, TRI); } void MIPrinter::print(const MCCFIInstruction &CFI, diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index c127c31aefb..8863ac23607 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -302,7 +302,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (Indexes) OS << '\t'; OS << " Live Ins:"; for (const auto &LI : LiveIns) { - OS << ' ' << PrintReg(LI.PhysReg, TRI); + OS << ' ' << printReg(LI.PhysReg, TRI); if (!LI.LaneMask.all()) OS << ':' << PrintLaneMask(LI.LaneMask); } diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 1fc4c07f9fd..1f55b8fa495 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -510,9 +510,9 @@ void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const { OS << "Function Live Ins: "; for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { - OS << PrintReg(I->first, TRI); + OS << printReg(I->first, TRI); if (I->second) - OS << " in " << PrintReg(I->second, TRI); + OS << " in " << printReg(I->second, TRI); if (std::next(I) != E) OS << ", "; } diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 26b440203f7..2d5307c78a5 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -391,7 +391,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, const TargetIntrinsicInfo *IntrinsicInfo) const { switch (getType()) { case MachineOperand::MO_Register: - OS << PrintReg(getReg(), TRI, getSubReg()); + OS << printReg(getReg(), TRI, getSubReg()); if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || isInternalRead() || isEarlyClobber() || isTied()) { @@ -520,7 +520,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, if (getRegMask()[MaskWord] & (1 << MaskBit)) { if (PrintRegMaskNumRegs < 0 || NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { - OS << " " << PrintReg(i, TRI); + OS << " " << printReg(i, TRI); NumRegsEmitted++; } NumRegsInMask++; @@ -2123,14 +2123,14 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, else OS << " " << TRI->getRegClassName(RC.get<const TargetRegisterClass *>()); - OS << ':' << PrintReg(VirtRegs[i]); + OS << ':' << printReg(VirtRegs[i]); for (unsigned j = i+1; j != VirtRegs.size();) { if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) { ++j; continue; } if (VirtRegs[i] != VirtRegs[j]) - OS << "," << PrintReg(VirtRegs[j]); + OS << "," << printReg(VirtRegs[j]); VirtRegs.erase(VirtRegs.begin()+j); } } diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index dfa0a4af334..a075543aecf 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -183,7 +183,7 @@ void MachineRegisterInfo::verifyUseList(unsigned Reg) const { MachineOperand *MO = &M; MachineInstr *MI = MO->getParent(); if (!MI) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use list MachineOperand " << MO << " has no parent instruction.\n"; Valid = false; @@ -192,19 +192,19 @@ void MachineRegisterInfo::verifyUseList(unsigned Reg) const { MachineOperand *MO0 = &MI->getOperand(0); unsigned NumOps = MI->getNumOperands(); if (!(MO >= MO0 && MO < MO0+NumOps)) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use list MachineOperand " << MO << " doesn't belong to parent MI: " << *MI; Valid = false; } if (!MO->isReg()) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " MachineOperand " << MO << ": " << *MO << " is not a register\n"; Valid = false; } if (MO->getReg() != Reg) { - errs() << PrintReg(Reg, getTargetRegisterInfo()) + errs() << printReg(Reg, getTargetRegisterInfo()) << " use-list MachineOperand " << MO << ": " << *MO << " is the wrong register\n"; Valid = false; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index ab2701b7294..6aaacb479fe 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1130,7 +1130,7 @@ void ScheduleDAGMILive::updatePressureDiffs( PDiff.addPressureChange(Reg, Decrement, &MRI); DEBUG( dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") " - << PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) + << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); dbgs() << " to "; PDiff.dump(*TRI); @@ -1138,7 +1138,7 @@ void ScheduleDAGMILive::updatePressureDiffs( } } else { assert(P.LaneMask.any()); - DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n"); + DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n"); // This may be called before CurrentBottom has been initialized. However, // BotRPTracker must have a valid position. We want the value live into the // instruction or live out of the block, so ask for the previous diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index 400f61d9bf2..453b47b71f7 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -1135,14 +1135,14 @@ computeInstrHeights(const MachineBasicBlock *MBB) { for (LiveInReg &LIR : TBI.LiveIns) { const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); LIR.Height = Heights.lookup(DefMI); - DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height); + DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height); } // Transfer the live regunits to the live-in list. for (SparseSet<LiveRegUnit>::const_iterator RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) { TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); - DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI) + DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' << RI->Cycle); } DEBUG(dbgs() << '\n'); diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 1c82f032c86..4f6eb428c8e 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -528,14 +528,14 @@ void MachineVerifier::report_context_liverange(const LiveRange &LR) const { } void MachineVerifier::report_context_vreg(unsigned VReg) const { - errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n'; + errs() << "- v. register: " << printReg(VReg, TRI) << '\n'; } void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const { if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) { report_context_vreg(VRegOrUnit); } else { - errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n'; + errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n'; } } @@ -1688,7 +1688,7 @@ void MachineVerifier::visitMachineFunctionAfter() { ++I) if (MInfo.regsKilled.count(*I)) { report("Virtual register killed in block, but needed live out.", &MBB); - errs() << "Virtual register " << PrintReg(*I) + errs() << "Virtual register " << printReg(*I) << " is used after the block.\n"; } } @@ -1721,13 +1721,13 @@ void MachineVerifier::verifyLiveVariables() { if (MInfo.vregsRequired.count(Reg)) { if (!VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block missing from AliveBlocks", &MBB); - errs() << "Virtual register " << PrintReg(Reg) + errs() << "Virtual register " << printReg(Reg) << " must be live through the block.\n"; } } else { if (VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block should not be in AliveBlocks", &MBB); - errs() << "Virtual register " << PrintReg(Reg) + errs() << "Virtual register " << printReg(Reg) << " is not needed live through the block.\n"; } } @@ -1746,7 +1746,7 @@ void MachineVerifier::verifyLiveIntervals() { if (!LiveInts->hasInterval(Reg)) { report("Missing live interval for virtual register", MF); - errs() << PrintReg(Reg, TRI) << " still has defs or uses\n"; + errs() << printReg(Reg, TRI) << " still has defs or uses\n"; continue; } diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index cda19b891b2..864d6d547ca 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -270,7 +270,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, IncomingReg = entry; reusedIncoming = true; ++NumReused; - DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi); + DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi); } else { const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); @@ -593,7 +593,7 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit) continue; if (ShouldSplit) { - DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" + DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#" << PreMBB->getNumber() << " -> BB#" << MBB.getNumber() << ": " << *BBI); } diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index 48bc8da3616..9da881005b5 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -322,8 +322,8 @@ void RegAllocFast::spillVirtReg(MachineBasicBlock::iterator MI, // instruction, not on the spill. bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI; LR.Dirty = false; - DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) - << " in " << PrintReg(LR.PhysReg, TRI)); + DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI) + << " in " << printReg(LR.PhysReg, TRI)); const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg); int FI = getStackSpaceFor(LRI->VirtReg, RC); DEBUG(dbgs() << " to stack slot #" << FI << "\n"); @@ -476,7 +476,7 @@ void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, /// \returns spillImpossible when PhysReg or an alias can't be spilled. unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { if (isRegUsedInInstr(PhysReg)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is already used in instr.\n"); return spillImpossible; } switch (unsigned VirtReg = PhysRegState[PhysReg]) { @@ -485,8 +485,8 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { case regFree: return 0; case regReserved: - DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " - << PrintReg(PhysReg, TRI) << " is reserved already.\n"); + DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " + << printReg(PhysReg, TRI) << " is reserved already.\n"); return spillImpossible; default: { LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); @@ -496,7 +496,7 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { } // This is a disabled register, add up cost of aliases. - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); unsigned Cost = 0; for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { MCPhysReg Alias = *AI; @@ -523,8 +523,8 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const { /// proper container for VirtReg now. The physical register must not be used /// for anything else when this is called. void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { - DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " - << PrintReg(PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to " + << printReg(PhysReg, TRI) << "\n"); PhysRegState[PhysReg] = LR.VirtReg; assert(!LR.PhysReg && "Already assigned a physreg"); LR.PhysReg = PhysReg; @@ -570,14 +570,14 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::allocVirtReg(MachineInstr &MI, } } - DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " + DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from " << TRI->getRegClassName(&RC) << "\n"); unsigned BestReg = 0; unsigned BestCost = spillImpossible; for (MCPhysReg PhysReg : AO) { unsigned Cost = calcSpillCost(PhysReg); - DEBUG(dbgs() << "\tRegister: " << PrintReg(PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n"); DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); // Cost is 0 when all aliases are already disabled. @@ -654,8 +654,8 @@ RegAllocFast::LiveRegMap::iterator RegAllocFast::reloadVirtReg(MachineInstr &MI, LRI = allocVirtReg(MI, LRI, Hint); const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); - DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " - << PrintReg(LRI->PhysReg, TRI) << "\n"); + DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " + << printReg(LRI->PhysReg, TRI) << "\n"); TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI); ++NumLoads; } else if (LRI->Dirty) { @@ -735,7 +735,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || (MO.getSubReg() && MI.readsVirtualRegister(Reg))) { if (ThroughRegs.insert(Reg).second) - DEBUG(dbgs() << ' ' << PrintReg(Reg)); + DEBUG(dbgs() << ' ' << printReg(Reg)); } } @@ -799,7 +799,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; unsigned Reg = MO.getReg(); if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; - DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI) << " as used in instr\n"); markRegUsedInInstr(Reg); } @@ -821,7 +821,7 @@ void RegAllocFast::dumpState() { dbgs() << "*"; break; default: { - dbgs() << '=' << PrintReg(PhysRegState[Reg]); + dbgs() << '=' << printReg(PhysRegState[Reg]); LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]); assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); if (I->Dirty) diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 557ec96a365..39676fed3d0 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -762,7 +762,7 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, // preferred register. if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) if (Order.isHint(Hint)) { - DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); + DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); EvictionCost MaxCost; MaxCost.setBrokenHints(1); if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { @@ -781,7 +781,7 @@ unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, if (!Cost) return PhysReg; - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost + DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost << '\n'); unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); return CheapReg ? CheapReg : PhysReg; @@ -811,7 +811,7 @@ unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { } if (PhysReg) DEBUG(dbgs() << "can reassign: " << VirtReg << " from " - << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) + << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI) << '\n'); return PhysReg; } @@ -1031,7 +1031,7 @@ void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, if (!Cascade) Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; - DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) + DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) << " interference: Cascade " << Cascade << '\n'); // Collect all interfering virtregs first. @@ -1123,8 +1123,8 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, // The first use of a callee-saved register in a function has cost 1. // Don't start using a CSR when the CostPerUseLimit is low. if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " - << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) + DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " + << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) << '\n'); continue; } @@ -1789,10 +1789,10 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, SpillPlacer->prepare(Cand.LiveBundles); BlockFrequency Cost; if (!addSplitConstraints(Cand.Intf, Cost)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); + DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); continue; } - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = "; + DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; MBFI->printBlockFreq(dbgs(), Cost)); if (Cost >= BestCost) { DEBUG({ @@ -1800,7 +1800,7 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, dbgs() << " worse than no bundles\n"; else dbgs() << " worse than " - << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; + << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; }); continue; } @@ -1838,7 +1838,7 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, // See splitCanCauseEvictionChain for detailed description of bad // eviction chain scenarios. DEBUG(dbgs() << "Best split candidate of vreg " - << PrintReg(VirtReg.reg, TRI) << " may "); + << printReg(VirtReg.reg, TRI) << " may "); if (!(*CanCauseEvictionChain)) DEBUG(dbgs() << "not "); DEBUG(dbgs() << "cause bad eviction chain\n"); @@ -1864,7 +1864,7 @@ unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { UsedCands.push_back(BestCand); Cand.IntvIdx = SE->openIntv(); - DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " + DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in " << B << " bundles, intv " << Cand.IntvIdx << ".\n"); (void)B; } @@ -2213,7 +2213,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' + DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore] << '-' << Uses[SplitAfter] << " i=" << MaxGap); @@ -2314,7 +2314,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) if (IntvMap[i] == 1) { setStage(LIS->getInterval(LREdit.get(i)), RS_Split2); - DEBUG(dbgs() << PrintReg(LREdit.get(i))); + DEBUG(dbgs() << printReg(LREdit.get(i))); } DEBUG(dbgs() << '\n'); } @@ -2503,7 +2503,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, Order.rewind(); while (unsigned PhysReg = Order.next()) { DEBUG(dbgs() << "Try to assign: " << VirtReg << " to " - << PrintReg(PhysReg, TRI) << '\n'); + << printReg(PhysReg, TRI) << '\n'); RecoloringCandidates.clear(); VirtRegToPhysReg.clear(); CurrentNewVRegs.clear(); @@ -2563,7 +2563,7 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, } DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to " - << PrintReg(PhysReg, TRI) << '\n'); + << printReg(PhysReg, TRI) << '\n'); // The recoloring attempt failed, undo the changes. FixedRegisters = SaveFixedRegisters; @@ -2626,7 +2626,7 @@ bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue, continue; } DEBUG(dbgs() << "Recoloring of " << *LI - << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n'); + << " succeeded with: " << printReg(PhysReg, TRI) << '\n'); Matrix->assign(*LI, PhysReg); FixedRegisters.insert(LI->reg); @@ -2793,8 +2793,8 @@ void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { Visited.insert(Reg); RecoloringCandidates.push_back(Reg); - DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '(' - << PrintReg(PhysReg, TRI) << ")\n"); + DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '(' + << printReg(PhysReg, TRI) << ")\n"); do { Reg = RecoloringCandidates.pop_back_val(); @@ -2815,7 +2815,7 @@ void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) { Matrix->checkInterference(LI, PhysReg))) continue; - DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI) + DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI) << ") is recolorable.\n"); // Gather the hint info. diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index c3bba16855e..5fa25d43e42 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -668,7 +668,7 @@ void RegAllocPBQP::spillVReg(unsigned VReg, const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); (void)TRI; - DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: " + DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: " << LRE.getParent().weight << ", New vregs: "); // Copy any newly inserted live intervals into the list of regs to @@ -677,7 +677,7 @@ void RegAllocPBQP::spillVReg(unsigned VReg, I != E; ++I) { const LiveInterval &LI = LIS.getInterval(*I); assert(!LI.empty() && "Empty spill range."); - DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " "); + DEBUG(dbgs() << printReg(LI.reg, &TRI) << " "); VRegsToAlloc.insert(LI.reg); } @@ -707,7 +707,7 @@ bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G, if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) { unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; - DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> " + DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> " << TRI.getName(PReg) << "\n"); assert(PReg != 0 && "Invalid preg selected."); VRM.assignVirt2Phys(VReg, PReg); @@ -864,7 +864,7 @@ static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); unsigned VReg = G.getNodeMetadata(NId).getVReg(); const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); - OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')'; + OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')'; }); } diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index dbf74a241be..b0eeb81f583 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -153,7 +153,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { DEBUG({ dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; for (unsigned I = 0; I != RCI.NumRegs; ++I) - dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); + dbgs() << ' ' << printReg(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); }); diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index ef95d648927..18f9ab4ae5f 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -569,7 +569,7 @@ bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP, // in IntB, we can merge them. if (ValS+1 != BS) return false; - DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI)); + DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI)); SlotIndex FillerStart = ValS->end, FillerEnd = BS->start; // We are about to delete CopyMI, so need to remove it as the 'instruction @@ -1638,8 +1638,8 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { // Enforce policies. if (CP.isPhys()) { - DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) - << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) + DEBUG(dbgs() << "\tConsidering merging " << printReg(CP.getSrcReg(), TRI) + << " with " << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'); if (!canJoinPhys(CP)) { // Before giving up coalescing, if definition of source is defined by @@ -1661,13 +1661,13 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { dbgs() << "\tConsidering merging to " << TRI->getRegClassName(CP.getNewRC()) << " with "; if (CP.getDstIdx() && CP.getSrcIdx()) - dbgs() << PrintReg(CP.getDstReg()) << " in " + dbgs() << printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName(CP.getDstIdx()) << " and " - << PrintReg(CP.getSrcReg()) << " in " + << printReg(CP.getSrcReg()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n'; else - dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in " - << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; + dbgs() << printReg(CP.getSrcReg(), TRI) << " in " + << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; }); } @@ -1758,11 +1758,11 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) { TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); DEBUG({ - dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) - << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; + dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) + << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; dbgs() << "\tResult = "; if (CP.isPhys()) - dbgs() << PrintReg(CP.getDstReg(), TRI); + dbgs() << printReg(CP.getDstReg(), TRI); else dbgs() << LIS->getInterval(CP.getDstReg()); dbgs() << '\n'; @@ -1797,7 +1797,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { return false; } if (RHS.overlaps(LIS->getRegUnit(*UI))) { - DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n'); + DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) << '\n'); return false; } } @@ -1867,7 +1867,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { // We're going to remove the copy which defines a physical reserved // register, so remove its valno, etc. - DEBUG(dbgs() << "\t\tRemoving phys reg def of " << PrintReg(DstReg, TRI) + DEBUG(dbgs() << "\t\tRemoving phys reg def of " << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n"); LIS->removePhysRegDefAt(DstReg, CopyRegIdx); @@ -2488,9 +2488,9 @@ void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) { assert(V.OtherVNI && "OtherVNI not assigned, can't merge."); assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion"); Assignments[ValNo] = Other.Assignments[V.OtherVNI->id]; - DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg) << ':' << ValNo << '@' + DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@' << LR.getValNumInfo(ValNo)->def << " into " - << PrintReg(Other.Reg) << ':' << V.OtherVNI->id << '@' + << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@' << V.OtherVNI->def << " --> @" << NewVNInfo[Assignments[ValNo]]->def << '\n'); break; @@ -2518,7 +2518,7 @@ bool JoinVals::mapValues(JoinVals &Other) { for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) { computeAssignment(i, Other); if (Vals[i].Resolution == CR_Impossible) { - DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg) << ':' << i + DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i << '@' << LR.getValNumInfo(i)->def << '\n'); return false; } @@ -2541,11 +2541,11 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other, // lanes escape the block. SlotIndex End = OtherI->end; if (End >= MBBEnd) { - DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.Reg) << ':' + DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':' << OtherI->valno->id << '@' << OtherI->start << '\n'); return false; } - DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.Reg) << ':' + DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':' << OtherI->valno->id << '@' << OtherI->start << " to " << End << '\n'); // A dead def is not a problem. @@ -2588,7 +2588,7 @@ bool JoinVals::resolveConflicts(JoinVals &Other) { assert(V.Resolution != CR_Impossible && "Unresolvable conflict"); if (V.Resolution != CR_Unresolved) continue; - DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg) << ':' << i + DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@' << LR.getValNumInfo(i)->def << '\n'); if (SubRangeJoin) return false; @@ -2699,7 +2699,7 @@ void JoinVals::pruneValues(JoinVals &Other, if (!EraseImpDef) EndPoints.push_back(Def); } - DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.Reg) << " at " << Def + DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def << ": " << Other.LR << '\n'); break; } @@ -2711,7 +2711,7 @@ void JoinVals::pruneValues(JoinVals &Other, // computeAssignment(), the value that was originally copied could have // been replaced. LIS->pruneValue(LR, Def, &EndPoints); - DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg) << " at " + DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at " << Def << ": " << LR << '\n'); } break; @@ -3019,7 +3019,7 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) { R.LaneMask = Mask; } } - DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg()) + DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS << '\n'); // Determine lanemasks of RHS in the coalesced register and merge subranges. @@ -3221,7 +3221,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const { continue; // Check that OtherReg interfere with DstReg. if (LIS->getInterval(OtherReg).overlaps(DstLI)) { - DEBUG(dbgs() << "Apply terminal rule for: " << PrintReg(DstReg) << '\n'); + DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) << '\n'); return true; } } @@ -3375,7 +3375,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { if (MRI->reg_nodbg_empty(Reg)) continue; if (MRI->recomputeRegClass(Reg)) { - DEBUG(dbgs() << PrintReg(Reg) << " inflated to " + DEBUG(dbgs() << printReg(Reg) << " inflated to " << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); ++NumInflated; diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp index 78c1d7e1576..b5c97fe77e1 100644 --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -97,7 +97,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { dumpRegSetPressure(MaxSetPressure, TRI); dbgs() << "Live In: "; for (const RegisterMaskPair &P : LiveInRegs) { - dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); + dbgs() << printVRegOrUnit(P.RegUnit, TRI); if (!P.LaneMask.all()) dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ' '; @@ -105,7 +105,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { dbgs() << '\n'; dbgs() << "Live Out: "; for (const RegisterMaskPair &P : LiveOutRegs) { - dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); + dbgs() << printVRegOrUnit(P.RegUnit, TRI); if (!P.LaneMask.all()) dbgs() << ':' << PrintLaneMask(P.LaneMask); dbgs() << ' '; diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp index b85eaabc4f9..758a81fa5f7 100644 --- a/llvm/lib/CodeGen/RegisterScavenging.cpp +++ b/llvm/lib/CodeGen/RegisterScavenging.cpp @@ -598,10 +598,10 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC, ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); Scavenged.Restore = &*std::prev(SpillBefore); LiveUnits.removeReg(Reg); - DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI) + DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) << " until " << *SpillBefore); } else { - DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n'); + DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); } return Reg; } diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index 19e0f30ecfc..72b7960f327 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -134,15 +134,15 @@ bool RenameIndependentSubregs::renameComponents(LiveInterval &LI) const { const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); SmallVector<LiveInterval*, 4> Intervals; Intervals.push_back(&LI); - DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses() + DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() << " equivalence classes.\n"); - DEBUG(dbgs() << PrintReg(Reg) << ": Splitting into newly created:"); + DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses; ++I) { unsigned NewVReg = MRI->createVirtualRegister(RegClass); LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg); Intervals.push_back(&NewLI); - DEBUG(dbgs() << ' ' << PrintReg(NewVReg)); + DEBUG(dbgs() << ' ' << printReg(NewVReg)); } DEBUG(dbgs() << '\n'); diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp index 7117b264c19..0635e8f41ee 100644 --- a/llvm/lib/CodeGen/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/ScheduleDAG.cpp @@ -80,7 +80,7 @@ raw_ostream &SDep::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const { case Data: OS << " Latency=" << getLatency(); if (TRI && isAssignedRegDep()) - OS << " Reg=" << PrintReg(getReg(), TRI); + OS << " Reg=" << printReg(getReg(), TRI); break; case Anti: case Output: diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 4f32fe4af52..dd30dc16378 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -528,7 +528,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { OS << LBB->getName() << " "; OS << (const void*)BBDN->getBasicBlock() << ">"; } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { - OS << ' ' << PrintReg(R->getReg(), + OS << ' ' << printReg(R->getReg(), G ? G->getSubtarget().getRegisterInfo() : nullptr); } else if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(this)) { diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp index 0adb8fa4988..59c5798ab49 100644 --- a/llvm/lib/CodeGen/SplitKit.cpp +++ b/llvm/lib/CodeGen/SplitKit.cpp @@ -1140,7 +1140,7 @@ bool SplitEditor::transferValues() { // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI. DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx - << '(' << PrintReg(Edit->get(RegIdx)) << ')'); + << '(' << printReg(Edit->get(RegIdx)) << ')'); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); // Check for a simply defined value that can be blitted directly. diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index ee63cd5ef19..4e28c4781c2 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -68,8 +68,8 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, continue; for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { - dbgs() << "Error: Super register " << PrintReg(*SR, this) - << " of reserved register " << PrintReg(Reg, this) + dbgs() << "Error: Super register " << printReg(*SR, this) + << " of reserved register " << printReg(Reg, this) << " is not reserved.\n"; return false; } @@ -84,7 +84,7 @@ bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, namespace llvm { -Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, +Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, unsigned SubIdx) { return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { if (!Reg) @@ -106,7 +106,7 @@ Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, }); } -Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { +Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { return Printable([Unit, TRI](raw_ostream &OS) { // Generic printout when TRI is missing. if (!TRI) { @@ -129,12 +129,12 @@ Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { }); } -Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { +Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { return Printable([Unit, TRI](raw_ostream &OS) { if (TRI && TRI->isVirtualRegister(Unit)) { OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); } else { - OS << PrintRegUnit(Unit, TRI); + OS << printRegUnit(Unit, TRI); } }); } @@ -429,6 +429,6 @@ bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, LLVM_DUMP_METHOD void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, const TargetRegisterInfo *TRI) { - dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; + dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; } #endif diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp index 97b8e0cef71..1533abde87e 100644 --- a/llvm/lib/CodeGen/VirtRegMap.cpp +++ b/llvm/lib/CodeGen/VirtRegMap.cpp @@ -140,8 +140,8 @@ void VirtRegMap::print(raw_ostream &OS, const Module*) const { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) { - OS << '[' << PrintReg(Reg, TRI) << " -> " - << PrintReg(Virt2PhysMap[Reg], TRI) << "] " + OS << '[' << printReg(Reg, TRI) << " -> " + << printReg(Virt2PhysMap[Reg], TRI) << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } @@ -149,7 +149,7 @@ void VirtRegMap::print(raw_ostream &OS, const Module*) const { for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) { - OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] + OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; } } |
