diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/ImplicitNullChecks.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachinePipeliner.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/RegisterPressure.cpp | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index 308b6d293d3..a10bb019926 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -198,7 +198,7 @@ class ImplicitNullChecks : public MachineFunctionPass { SuitabilityResult isSuitableMemoryOp(MachineInstr &MI, unsigned PointerReg, ArrayRef<MachineInstr *> PrevInsts); - /// Return true if \p FaultingMI can be hoisted from after the the + /// Return true if \p FaultingMI can be hoisted from after the /// instructions in \p InstsSeenSoFar to before them. Set \p Dependence to a /// non-null value if we also need to (and legally can) hoist a depedency. bool canHoistInst(MachineInstr *FaultingMI, unsigned PointerReg, diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 73f0bff3a91..3cce7b3649b 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -138,7 +138,7 @@ static cl::opt<bool> EnableSWPOptSize("enable-pipeliner-opt-size", /// A command line argument to limit minimum initial interval for pipelining. static cl::opt<int> SwpMaxMii("pipeliner-max-mii", - cl::desc("Size limit for the the MII."), + cl::desc("Size limit for the MII."), cl::Hidden, cl::init(27)); /// A command line argument to limit the number of stages in the pipeline. @@ -313,7 +313,7 @@ public: /// Return the latest time an instruction my be scheduled. int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; } - /// The mobility function, which the the number of slots in which + /// The mobility function, which the number of slots in which /// an instruction may be scheduled. int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node); } @@ -970,7 +970,7 @@ static unsigned getInitPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) { return 0; } -/// Return the Phi register value that comes the the loop block. +/// Return the Phi register value that comes the loop block. static unsigned getLoopPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) { for (unsigned i = 1, e = Phi.getNumOperands(); i != e; i += 2) if (Phi.getOperand(i + 1).getMBB() == LoopBB) diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index e492c481a54..e4801c48efd 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -399,7 +399,7 @@ class RAGreedy : public MachineFunctionPass, /// obtained from the TargetSubtargetInfo. bool EnableLocalReassign; - /// Enable or not the the consideration of the cost of local intervals created + /// Enable or not the consideration of the cost of local intervals created /// by a split candidate when choosing the best split candidate. bool EnableAdvancedRASplitCost; @@ -1448,7 +1448,7 @@ bool RAGreedy::splitCanCauseEvictionChain(unsigned Evictee, getCheapestEvicteeWeight(Order, LIS->getInterval(Evictee), Cand.Intf.first(), Cand.Intf.last(), &MaxWeight); - // The bad eviction chain occurs when either the split candidate the the + // The bad eviction chain occurs when either the split candidate the // evited reg or one of the split artifact will evict the evicting reg. if ((PhysReg != Cand.PhysReg) && (PhysReg != FutureEvictedPhysReg)) return false; diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp index 9ac810c7c72..bc1af1594c2 100644 --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -587,7 +587,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS, for (auto I = Defs.begin(); I != Defs.end(); ) { LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit, Pos.getDeadSlot()); - // If the the def is all that is live after the instruction, then in case + // If the def is all that is live after the instruction, then in case // of a subregister def we need a read-undef flag. unsigned RegUnit = I->RegUnit; if (TargetRegisterInfo::isVirtualRegister(RegUnit) && |
